Power reduction through work reuse

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Power reduction through work reuse

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 340 - 345

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Emil Talpes	Carnegie Mellon University, ECE Department, 5000 Forbes Ave, Pittsburgh, PA
Diana Marculescu	Carnegie Mellon University, ECE Department, 5000 Forbes Ave, Pittsburgh, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 13, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Black and J. P. Shen - "TurboScalar: A High Frequency, High IPC Microarchitecture" - International Symposium on Computer Architecture, June 2000
	2	Bryan Black , Bohuslav Rychlik , John Paul Shen, The block-based trace cache, Proceedings of the 26th annual international symposium on Computer architecture, p.196-207, May 01-04, 1999, Atlanta, Georgia, United States
	3	B. Black, J. P. Shen - "Scalable Register Renaming via the Quack Register File" - Technical Report CMuART-2000-01
	4	Eric Rotenberg , Steve Bennett , James E. Smith, A Trace Cache Microarchitecture and Evaluation, IEEE Transactions on Computers, v.48 n.2, p.111-120, February 1999 [doi>10.1109/12.752652]
	5	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224120]
	6	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]
	7	T. D. Burd , R. W. Brodersen, Energy efficient CMOS microprocessor design, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.288, January 04-07, 1995
	8	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	9	Nikolaos Bellas Ibrahim Hajj , George Stamoulis , N. Bellas , C. Polychronopoulos, Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors, Proceedings of the 1998 international symposium on Low power electronics and design, p.70-75, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280788]
	10	F. Theeuwen, E. Seelen - "Power Reduction Through Clock Gating by Symbolic Manipulation" - Workshop on Logic and Architecture Synthesis, 1996
	11	T. Austin, "The SimpleScalar Architectural Research Tool Set, Version 2.0" - Computer Sciences Technical Report, June 1997
	12	David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
	13	INTEL Corp - US Patent US6170038 "Trace based instruction caching"
	14	Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
	15	SPEC Benchmarks - www.spec.com
	16	Pentium 4 Microarchitecture - P. De Mone - http://www.realworldtech.com

CITED BY 7

	Madhavi Valluri , Lizy John , Heather Hanson, Exploiting compiler-generated schedules for energy savings in high-performance processors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Emil Talpes , Diana Marculescu, Impact of technology scaling on energy aware execution cache-based microarchitectures, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Emil Talpes , Diana Marculescu, Execution cache-based microarchitecture power-efficient superscalar processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.14-26, January 2005
	Madhavi G. Valluri , Lizy K. John , Kathryn S. McKinley, Low-power, low-complexity instruction issue using compiler assistance, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
	Weiyu Tang , Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau, A predictive decode filter cache for reducing power consumption in embedded processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.2, p.14-es, April 2007
	Emil Talpes , Diana Marculescu, Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines, ACM SIGARCH Computer Architecture News, v.33 n.2, p.310-321, May 2005
	Frederico Pratas , Georgi Gaydadjiev , Mladen Berekovic , Leonel Sousa , Stefanos Kaxiras, Low power microarchitecture with instruction reuse, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy