Design methodology and optimization strategy for dual-VTH scheme using commercially available tools

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Design methodology and optimization strategy for dual-VTH scheme using commercially available tools

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 283 - 286

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Masayuki Hirabayashi	Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505 Japan
Koichi Nose	Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505 Japan
Takayasu Sakurai	Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505 Japan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 3

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, "1-V power supply high-speed digital circuits technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp.847-854, Aug. 1995.
	2	T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz 10-mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE J. Solid-State Circuits, vol.31, no.11, PP.1770-1779, Nov. 1996.
	3	Qi Wang , Sarma B. K. Vrudhula, Static power optimization of deep submicron CMOS circuits for dual VT technology, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.490-496, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289076]
	4	Design Compiler Reference Manual, Synopsys Inc., 1997.
	5	Koichi Nose , Takayasu Sakurai, Optimization of VDD and VTH for low-power and high speed applications, Proceedings of the 2000 conference on Asia South Pacific design automation, p.469-474, January 2000, Yokohama, Japan [doi>10.1145/368434.368755]
	6	Apollo user guide, Avant! Co., 1998.
	7	Diva interactive verification reference manual, Cadence Design Systems Inc., 1997.

CITED BY 3

	Michael Liu , Wei-Shen Wang , Michael Orshansky, Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California
	Hsinwei Chou , Yu-Hao Wang , Charlie Chung-Ping Chen, Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China