Selectively clocked skewed logic (SCSL)

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Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 267 - 270

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Naran Sirisantana	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Aiqun Cao	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Shawn Davidson	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Cheng Kok Koh	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Kaushik Roy	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 13, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. D. Meindl, Low power Microelectronics: Retrospect and Prospect, Proceedings of the IEEE, v 83, n 4, pp. 619, 1995.
	2	A. P. Chandrakasan, S. Sheng and R. W. Brodersen, Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, v 27, n 4, pp. 473, 1992
	3	D. Somasekhar, Power and dynamic noise considerations in high performance CMOS VLSI design, Ph.D. Thesis, Purdue University, August 1999.
	4	Min Zhao , Sachin S. Sapatnekar, Technology mapping for domino logic, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.248-251, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288621]
	5	Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.241, September 17-20, 2000
	6	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	7	S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, Inc., 1981.
	8	E. M. Sentovich, et al., SIS: A System Sequential Circuit Synthesis, Electronics Research Laboratory Memorandum No. UCB/ERL M92141, University of California, Berkeley, 1992.
	9	S. M. Reddy, Complete test sets for logic functions, IEEE Transaction on Computers, C-22(11): 1016-1020, November 1973.
	10	Yuan Taur , Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, New York, NY, 1998

CITED BY 3

	Naran Sirisantana , Bipul C. Paul , Kaushik Roy, Enhancing Yield at the End of the Technology Roadmap, IEEE Design & Test, v.21 n.6, p.563-571, November 2004
	Aiqun Cao , Naran Sirisantana , Cheng-Kok Koh , Kaushik Roy, Synthesis of skewed logic circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.205-228, April 2005
	Aiqun Cao , Naran Sirisantana , Cheng-Kok Koh , Kaushik Roy, Integer linear programming-based synthesis of skewed logic circuits, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan