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Energy: efficient instruction dispatch buffer design for superscalar processors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 237 - 242

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Gurhan Kucuk	Department of Computer Science, State University of New York, Binghamton, NY
Kanad Ghose	Department of Computer Science, State University of New York, Binghamton, NY
Dimitry V. Ponomarev	Department of Computer Science, State University of New York, Binghamton, NY
Peter M. Kogge	Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 24, Citation Count: 11

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David Brooks , Margaret Martonosi, Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.13, January 09-12, 1999
	2	Burger, D., and Austin, T. M., "The SimpleScalar Tool Set: Version 2.0", Tech. Report, Dept. of CS, Univ. of Wisconsin, Madison, June 1997 and documentation for all Simplescalar releases (through version 3.0).
	3	Alper Buyuktosunoglu , Stanley Schuster , David Brooks , Pradip Bose , Peter W. Cook , David H. Albonesi, An Adaptive Issue Queue for Reduced Power at High Performance, Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers, p.25-39, November 12, 2000
	4	Ramon Canal , Antonio González , James E. Smith, Very low power pipelines using significance compression, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.181-190, December 2000, Monterey, California, United States [doi>10.1145/360128.360147]
	5	Kanad Ghose, Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.231-233, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344604]
	6	Ghose, K., Ponomarev, D., Kucuk, G., Flinders, A., Kogge, P., and Toomarian N.,"Exploiting Bit-slice Inactivities for Reducing Energy Requirements of Superscalar Processors," in Proc. of Kool Chips Workshop, Micro-33, 2000.
	7	Palacharla, S., Jouppi, N. P. and Smith, J. E., "Quantifying the complexity of superscalar processors", Tech. Report 96-1308, Dept. of CS, Univ. of Wisconsin, Madison, 1996.
	8	Ponomarev, D., Kucuk, G. and Ghose, K., "Dynamic Allocation of Datapath Resources for Low Power", to appear in the Proc. of the Workshop on Complexity-Effective Architectures, held in conjunction with ISCA, June 01.
	9	Luis Villa , Michael Zhang , Krste Asanović, Dynamic zero compression for cache energy reduction, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.214-220, December 2000, Monterey, California, United States [doi>10.1145/360128.360150]

CITED BY 11

	Gurhan Kucuk , Dmitry Ponomarev , Kanad Ghose, Low-complexity reorder buffer architecture, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
	Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose, Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Alper Buyuktosunoglu , David H. Albonesi , Pradip Bose , Peter W. Cook , Stanley E. Schuster, Tradeoffs in power-efficient issue queue design, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Dan Ernst , Todd Austin, Efficient dynamic scheduling through tag elimination, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Dmitry V. Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose , Peter M. Kogge, Energy-efficient issue queue design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.789-800, October 2003
	Dmitry Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose, Power efficient comparators for long arguments in superscalar processors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Gurhan Kucuk , Dmitry V. Ponomarev , Oguz Ergin , Kanad Ghose, Complexity-Effective Reorder Buffer Designs for Superscalar Processors, IEEE Transactions on Computers, v.53 n.6, p.653-665, June 2004
	Energy Efficient Comparators for Superscalar Datapaths, IEEE Transactions on Computers, v.53 n.7, p.892-904, July 2004
	Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose, Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency, IEEE Transactions on Computers, v.55 n.2, p.199-213, February 2006
	Marco A. Ramirez , Adrian Cristal , Mateo Valero , Alexander V. Veidenbaum , Luis Villa, A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, v.1 n.4, p.153-161, December 2004
	Gabriel H. Loh, A modular 3d processor for flexible product design and technology migration, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy