| A system-level energy minimization approach using datapath width optimization |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2001 international symposium on Low power electronics and design
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Huntington Beach, California, United States
Pages: 231 - 236
Year of Publication: 2001
ISBN:1-58113-371-5
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Authors
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Yun Cao
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Department of Computer Science and Communication Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka 816-8580, Japan
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Hiroto Yasuura
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Department of Computer Science and Communication Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka 816-8580, Japan
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Downloads (6 Weeks): 5, Downloads (12 Months): 23, Citation Count: 7
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A.Inoue,H.Tomiyama,T.Okuma,H.Kanbara and H.Yasuura,"Language and Compiler for Optimizing Datapath Width of Embedded Systems ",IEICE Trans.Fundamentals,Vol.E81-A,No.12,pp. 2595-2604,Dec.1998.
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F.N.Eko,A.Inoue,H.Tomiyama,H.Yasuura, "Soft-Core Processor Architecture for Embedded System Design ",IEICE Trans.on Electronics, Vol.E81-C No.9,pp1416-1423,Sep.1998.
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E.N.Eko and H.Yasuura,"A Cycle-Accurate Simulator Toolkit for Soft-Core Processors ",Proc.of Asia Paci .c Conference on cHip Design Languages (APCHDL '99),pp.11-16,October 1999.
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B.Shackleford,M.Yasuda,E.Okushi,H.Koizumi, H.Tomiyama,H.Yasuura,"Embedded System Cost Optimization via Data Path Width Adjustment ", IEICE Trans.Information and Systems,Vol.E80-D, No.10,pp974-981,October.1997.
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A.Inoue,T.Ishihara and H.Yasuura,"Flexible system lsi for embedded systems and its optimization techniques ",Journal of Design Automation for Embedded System,5(2),2000.
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Luca Benini , Robin Hodgson , Polly Siegel, System-level power estimation and optimization, Proceedings of the 1998 international symposium on Low power electronics and design, p.173-178, August 10-12, 1998, Monterey, California, United States
[doi> 10.1145/280756.280881]
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T.Sato,M.Nagamatsu,H.Tago,"Power and Performance Simulator:ESP and its Application for 100 MIPS/W Class RISC Design ",IEEE Proc.of Symposium on Low Power Electronics and Design, pp.46-47,1994.
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Inki Hong , Darko Kirovski , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava, Power optimization of variable voltage core-based systems, Proceedings of the 35th annual conference on Design automation, p.176-181, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277088]
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CITED BY 7
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Jason Cong , Yiping Fan , Guoling Han , Yizhou Lin , Junjuan Xu , Zhiru Zhang , Xu Cheng, Bitwidth-aware scheduling and binding in high-level synthesis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
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