| Low power pipelining of linear systems: a common operand centric approach |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2001 international symposium on Low power electronics and design
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Huntington Beach, California, United States
Pages: 225 - 230
Year of Publication: 2001
ISBN:1-58113-371-5
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Downloads (6 Weeks): 0, Downloads (12 Months): 6, Citation Count: 3
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REFERENCES
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G. Goossens , J. Vandewlle , H. De Man, Loop optimization in register-transfer scheduling for DSP-systems, Proceedings of the 26th ACM/IEEE conference on Design automation, p.826-831, June 25-28, 1989, Las Vegas, Nevada, United States
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Brodersen, et al, "An integrated CAD system for algorithm-specific IC design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 4, pp. 447-463, April 1991.
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C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6:5-35, 1991.
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CITED BY 3
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Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006
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Meikang Qiu , Meiqin Liu , Hao Li , Hung-Chung Huang , Wenyuan Li , Jiande Wu, Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture, Journal of Signal Processing Systems, v.57 n.3, p.363-379, December 2009
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