Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Full text

Pdf (271 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 207 - 212

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

A. Keshavarzi	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
S. Ma	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
S. Narendra	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
B. Bloechel	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
K. Mistry	Portland Technology Development, Intel Corporation, Hillsboro, OR
T. Ghani	Portland Technology Development, Intel Corporation, Hillsboro, OR
S. Borkar	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
V. De	Microprocessor Research Labs, Intel Corporation, Hillsboro, OR

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 78, Citation Count: 29

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/383082.383135 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. Kuroda et. al., IEEE JSSC, Nov. 1996, pp. 1770-1779
	2	T. Kobayashi et. al., 1994 Proc. of CICC, pp. 271-274
	3	K. Seta et. al., 1995 ISSCC Tech. Dig., pp. 318-319
	4	S. Thompson et. al., 1997 Symp. VLSI Tech., pp. 69-70
	5	Ali Keshavarzi , Kaushik Roy , Charles F. Hawkins, Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs, Proceedings of the IEEE International Test Conference, p.146-155, November 03-05, 1997
	6	Siva Narendra , Dimitri Antoniadis , Vivek De, Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation, Proceedings of the 1999 international symposium on Low power electronics and design, p.229-232, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313932]
	7	Ali Keshavarzi , Siva Narendra , Shekhar Borkar , Charles Hawkins , Kaushik Roy , Vivek De, Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's, Proceedings of the 1999 international symposium on Low power electronics and design, p.252-254, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313937]
	8	A. Keshavarzi et. al., 1999 NASA Symp., pp. 2.3.1-2.3.9
	9	V. De et. al., 1999 ISLPED, pp. 163-168
	10	T. Ghani et. al., 2000 Symp. VLSI Tech., pp. 174-175
	11	L. Su et. al., Symp. VLSI Tech., pp. 18-19, 1998.

CITED BY 29

	Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar, Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Jason H. Anderson , Farid N. Najm , Tim Tuan, Active leakage power optimization for FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Siva Narendra , Vivek De , Shekhar Borkar , Dimitri Antoniadis , Anantha Chandrakasan, Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Chris H. Kim , Kaushik Roy, Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Kiyoo Itoh, Low-voltage memories for power-aware systems, Proceedings of the 2002 international symposium on Low power electronics and design, p.1-6, August 12-14, 2002, Monterey, California, USA
	Davood Shahrjerdi , Bahman Hekmatshoar , Ali Khakifirooz , Ali Afzali-Kusha, Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits, Integration, the VLSI Journal, v.38 n.3, p.505-513, January 2005
	Y.-F. Tsai , D. Duarte , N. Vijaykrishnan , M. J. Irwin, Implications of technology scaling on leakage reduction techniques, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Sagar S. Sabade , Duncan M. Walker, I_DDX-based test methods: A survey, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.2, p.159-198, April 2004
	Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Y. Nakagome , M. Horiguchi , T. Kawahara , K. Itoh, Review and future prospects of low-voltage RAM circuits, IBM Journal of Research and Development, v.47 n.5-6, p.525-552, September 2003
	Siva G. Narendra, Challenges and design choices in nanoscale CMOS, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.1, p.7-49, April 2005
	Andrea Lodi , Luca Ciccarelli , Roberto Giansante, Combining low-leakage techniques for FPGA routing design, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Mauro Olivieri , Giuseppe Scotti , Alessandro Trifiletti, A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.630-638, May 2005
	Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Rabiul Islam , Adam Brand , Dave Lippincott, Low power SRAM techniques for handheld products, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Swarup Bhunia , Nilanjan Banerjee , Qikai Chen , Hamid Mahmoodi , Kaushik Roy, A novel synthesis approach for active leakage power reduction using dynamic supply gating, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Ruchir Puri , Leon Stok , Subhrajit Bhattacharya, Keeping hot chips cool, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Anirudh Devgan, Achieving continuous V_T performance in a dual V_T process, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Steven M. Martin , Krisztian Flautner , Trevor Mudge , David Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.721-725, November 10-14, 2002, San Jose, California
	Davood Shahrjerdi , Bahman Hekmatshoar , Ali Afzali-Kusha , Ali Khakifirooz, Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	S. Hanson , B. Zhai , K. Bernstein , D. Blaauw , A. Bryant , L. Chang , K. K. Das , W. Haensch , E. J. Nowak , D. M. Sylvester, Ultralow-voltage, minimum-energy CMOS, IBM Journal of Research and Development, v.50 n.4/5, p.469-490, July 2006
	Murari Mani , Ashish K. Sing , Michael Orshansky, Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Dennis Sylvester , Kanak Agarwal , Saumil Shah, Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization, Integration, the VLSI Journal, v.41 n.3, p.319-339, May, 2008
	Le Yan , Jiong Luo , Niraj K. Jha, Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.30, November 09-13, 2003
	Yingmin Li , Dharmesh Parikh , Yan Zhang , Karthik Sankaranarayanan , Mircea Stan , Kevin Skadron, State-Preserving vs. Non-State-Preserving Leakage Control in Caches, Proceedings of the conference on Design, automation and test in Europe, p.10022, February 16-20, 2004
	W. Zhang , M. Kandemir , N. Vijaykrishnan , M. J. Irwin , V. De, Compiler Support for Reducing Leakage Energy Consumption, Proceedings of the conference on Design, Automation and Test in Europe, p.11146, March 03-07, 2003
	Mesut Meterelliyoz , Kaushik Roy, Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Keivan Navi , Mehrdad Maeen , Vahid Foroutan , Somayeh Timarchi , Omid Kavehei, A novel low-power full-adder cell for low voltage, Integration, the VLSI Journal, v.42 n.4, p.457-467, September, 2009
	Bin Li , Li-Shiuan Peh , Priyadarsan Patra, Impact of Process and Temperature Variations on Network-on-Chip Design Exploration, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.117-126, April 07-10, 2008