Scaling of stack effect and its application for leakage reduction

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Scaling of stack effect and its application for leakage reduction

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 195 - 200

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Siva Narendra	Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR
Vivek De	Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR
Dimitri Antoniadis	Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA
Anantha Chandrakasan	Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA
Shekhar Borkar	Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 26, Downloads (12 Months): 108, Citation Count: 29

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Sagar S. Sabade , Duncan M. Walker, I_DDX-based test methods: A survey, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.2, p.159-198, April 2004
	Sung-Mo Kang, Elements of low power design for integrated systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Jason H. Anderson , Farid N. Najm , Tim Tuan, Active leakage power optimization for FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Y.-F. Tsai , D. Duarte , N. Vijaykrishnan , M. J. Irwin, Implications of technology scaling on leakage reduction techniques, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Narender Hanchate , Nagarajan Ranganathan, LECTOR: a technique for leakage reduction in CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.196-205, February 2004
	Volkan Kursun , Eby G. Friedman, Sleep switch dual threshold voltage domino logic with reduced standby leakage current, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.5, p.485-496, May 2004
	Y. Nakagome , M. Horiguchi , T. Kawahara , K. Itoh, Review and future prospects of low-voltage RAM circuits, IBM Journal of Research and Development, v.47 n.5-6, p.525-552, September 2003
	Siva G. Narendra, Challenges and design choices in nanoscale CMOS, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.1, p.7-49, April 2005
	Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Mauro Olivieri , Giuseppe Scotti , Alessandro Trifiletti, A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.630-638, May 2005
	James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California
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	Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang , Peter W. Cook , Richard B. Brown, New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Keunwoo Kim , Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang, Nanoscale CMOS circuit leakage power reduction by double-gate device, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Nam Sung Kim , Krisztian Flautner , David Blaauw , Trevor Mudge, Circuit and microarchitectural techniques for reducing cache leakage power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.167-184, February 2004
	Harmander Singh , Kanak Agarwal , Dennis Sylvester , Kevin J. Nowka, Enhanced leakage reduction techniques using intermediate strength power gating, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1215-1224, November 2007
	Jacopo Giorgetti , Giuseppe Scotti , Andrea Simonetti , Alessandro Trifiletti, Analysis of data dependence of leakage current in CMOS cryptographic hardware, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Simone Medardoni , Davide Bertozzi , Enrico Macii, Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
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