Low power address encoding using self-organizing lists

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Low power address encoding using self-organizing lists

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 188 - 193

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Mahesh Mamidipaka	Center for Embedded Systems, University of California, Irvine, Irvine, CA
Dan Hirschberg	Dept. of ICS, University of California, Irvine, Irvine, CA
Nikil Dutt	Center for Embedded Systems, University of California, Irvine, Irvine, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Benini, A. Macci, E. Macii, M. Poncino, and R. Scarsi. Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Transactions on Computer Aided Design of Circuits and Systems, 19, 2000.
	2	Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
	3	A. P. Chandrakasan and R. W. Broderson. Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE, 83:498,523, 1995.
	4	Wei-Chung Cheng , Massoud Pedram, Low power techniques for address encoding and memory allocation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.245-250, January 2001, Yokohama, Japan [doi>10.1145/370155.370334]
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	8	M. N. Mahesh, D. Hirschberg, and N. Dutt. Encoding techniques for low power address buses. Technical Report #01-22, University of California, Irvine, 2001, http://www.ics.uci.edu/~maheshmn/encoding tr.doc.
	9	Enric Musoll , Tomás Lang , Jordi Cortadella, Working-zone encoding for reducing the energy in microprocessor address buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.568-572, Dec. 1998 [doi>10.1109/92.736129]
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	12	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997 [doi>10.1023/A:1007907110303]
	13	Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.212-221, June 1999 [doi>10.1109/92.766748]
	14	Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
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CITED BY 9

	Mahesh Mamidipaka , Nikil Dutt , Dan Hirschberg, Efficient power reduction techniques for time multiplexed address buses, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Mahesh N. Mamidipaka , Daniel S. Hirschberg , Nikil D. Dutt, Adaptive low-power address encoding techniques using self-organizing lists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.827-834, October 2003
	Peter Petrov , Alex Orailoglu, Low-power instruction bus encoding for embedded processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.8, p.812-826, August 2004
	Preeti Ranjan Panda, Abridged addressing: a low power memory addressing strategy, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Peter Petrov , Alex Orailoglu, Low-power data memory communication for application-specific embedded processors, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Yazdan Aghaghiri , Massoud Pedram , Farzan Fallah, Reducing transitions on memory buses using sector-based encoding technique, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Peter Petrov , Alex Orailoglu, Power Efficiency through Application-Specific Instruction Memory Transformations, Proceedings of the conference on Design, Automation and Test in Europe, p.10030, March 03-07, 2003
	M. Saneei , A. Afzali-Kusha , Z. Navabi, Sign Bit Reduction Encoding For Low Power Applications, Journal of Signal Processing Systems, v.57 n.3, p.321-329, December 2009
	Dinesh C. Suresh , Banit Agrawal , Jun Yang , Walid Najjar, Energy-efficient encoding techniques for off-chip data buses, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.2, p.1-23, January 2009