| Low power address encoding using self-organizing lists |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2001 international symposium on Low power electronics and design
table of contents
Huntington Beach, California, United States
Pages: 188 - 193
Year of Publication: 2001
ISBN:1-58113-371-5
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Authors
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Mahesh Mamidipaka
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Center for Embedded Systems, University of California, Irvine, Irvine, CA
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Dan Hirschberg
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Dept. of ICS, University of California, Irvine, Irvine, CA
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Nikil Dutt
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Center for Embedded Systems, University of California, Irvine, Irvine, CA
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Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 8
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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L. Benini, A. Macci, E. Macii, M. Poncino, and R. Scarsi. Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Transactions on Computer Aided Design of Circuits and Systems, 19, 2000.
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A. P. Chandrakasan and R. W. Broderson. Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE, 83:498,523, 1995.
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M. N. Mahesh, D. Hirschberg, and N. Dutt. Encoding techniques for low power address buses. Technical Report #01-22, University of California, Irvine, 2001, http://www.ics.uci.edu/~maheshmn/encoding tr.doc.
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