Low-energy for deep-submicron address buses

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Low-energy for deep-submicron address buses

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 176 - 181

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Luca Macchiarulo	Politecnico di Torino, Torino, Italy
Enrico Macii	Politecnico di Torino, Torino, Italy
Massimo Poncino	Politecnico di Torino, Torino, Italy

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 11, Citation Count: 12

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
	2	Mircea R. Stan , Wayne P. Burleson, Low-power encodings for global communication in CMOS VLSI, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.444-455, Dec. 1997 [doi>10.1109/92.645071]
	3	Youngsoo Shin , Soo-IK Chae , Kiyoung Choi, Partial bus-invert coding for power optimization of system level bus, Proceedings of the 1998 international symposium on Low power electronics and design, p.127-129, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280829]
	4	L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi, "Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces," IEEE Trans. on CAD, Vol. 19 No. 9, pp. 969-980, Sept. 2000.
	5	Ching-Long Su , Chi-Ying Tsui , Alvin M. Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design & Test, v.11 n.4, p.24-30, October 1994 [doi>10.1109/54.329448]
	6	Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
	7	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Some Issues in Gray Code Addressing, Proceedings of the 6th Great Lakes Symposium on VLSI, p.178, March 22-23, 1996
	8	L. Benini , G. De Micheli , E. Macii , D. Sciuto , C. Silvano, Address bus encoding techniques for system-level power optimization, Proceedings of the conference on Design, automation and test in Europe, p.861-867, February 23-26, 1998, Le Palais des Congrés de Paris, France
	9	Luca Benini , Giovanni De Mecheli , Enrico Macii , Massimo Poncino , Stefano Quer, Power optimization of core-based systems by address bus encoding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.554-562, Dec. 1998 [doi>10.1109/92.736127]
	10	Enric Musoll , Tomás Lang , Jordi Cortadella, Working-zone encoding for reducing the energy in microprocessor address buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.568-572, Dec. 1998 [doi>10.1109/92.736129]
	11	Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.2, p.212-221, June 1999 [doi>10.1109/92.766748]
	12	S. Ramprasad, N. R. Shanbhag, I. N. Hajj, "Signal Coding for Low Power: Fundamental Limits and Practical Realizations," IEEE Trans. on CAS II, Vol. 46, No. 2, pp. 923-929, Jul. 1999.
	13	Paul P. Sotiriadis , Anantha Chandrakasan, Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	14	Ki Wook Kim , Kwang Hyun Baek , Naresh Shanbhag , C. L. Liu , Sung Mo Kang, Coupling-driven signal encoding scheme for low-power interface design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	15	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	16	S. Lin, "Computer Solution of the Traveling Salesman Problem," Bell Systems Technical Journal, Vol. 44, No. 10, pp. 2245-2269, Dec. 1965.

CITED BY 12

	Enrico Macii , Massimo Poncino , Sabino Salerno, Combining wire swapping and spacing for low-power deep-submicron buses, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Tiehan Lv , Jörg Henkel , Haris Lekatsas , Wayne Wolf, A dictionary-based en/decoding scheme for low-power data buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.943-951, October 2003
	Ismail Kadayif , Mahmut Kandemir , Guilin Chen , Ozcan Ozturk , Mustafa Karakoy , Ugur Sezer, Optimizing Array-Intensive Applications for On-Chip Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.5, p.396-411, May 2005
	Sri Parameswaran , Jörg Henkel , Haris Lekastas, Multi-parametric improvements for embedded systems using code-placement and address bus coding, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram, BEAM: bus encoding based on instruction-set-aware memories, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Masanori Muroyama , Kosuke Tarumi , Koji Makiyama , Hiroto Yasuura, A variation-aware low-power coding methodology for tightly coupled buses, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yazdan Aghaghiri , Massoud Pedram , Farzan Fallah, Reducing transitions on memory buses using sector-based encoding technique, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Yan Zhang , John Lach , Kevin Skadron , Mircea R. Stan, Odd/even bus invert with two-phase transfer for buses with coupling, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Edwin Naroska , Shanq-Jang Ruan , Uwe Schwiegelshohn, Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.4, p.421-425, April 2006
	Krishnan Sundaresan , Nihar R. Mahapatra, Value-based bit ordering for energy optimization of on-chip global signal buses, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Karthik Duraisami , Enrico Macii , Massimo Poncino, Energy efficiency bounds of pulse-encoded buses, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Siu-Kei Wong , Chi-Ying Tsui, Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus, Proceedings of the conference on Design, automation and test in Europe, p.10130, February 16-20, 2004