Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

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Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 147 - 152

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

James Tschanz	Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR
Siva Narendra	Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR
Zhanping Chen	Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR
Shekhar Borkar	Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR
Manoj Sachdev	Department of ECE, University of Waterloo, Canada
Vivek De	Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 54, Citation Count: 15

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	6	A. Gago et. al., IEEE JSSC, pp. 400-402, March 1999

CITED BY 15

	Nikola Nedovic , Marko Aleksic , Vojin G. Oklobdzija, Conditional pre-charge techniques for power-efficient dual-edge clocking, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Victor Zyuban , Stephen V. Kosonocky, Low power integrated scan-retention mechanism, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Victor Zyuban, Optimization of scannable latches for low energy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.778-788, October 2003
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.185-195, February 2004
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	V. G. Oklobdzija, Clocking and clocked storage elements in a multi-gigahertz environment, IBM Journal of Research and Development, v.47 n.5-6, p.567-583, September 2003
	Peiyi Zhao , Tarek K. Darwish , Magdy A. Bayoumi, High-performance and low-power conditional discharge flip-flop, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.5, p.477-484, May 2004
	Sarvesh H. Kulkarni , Dennis Sylvester, High performance level conversion for dual VDD design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.926-936, September 2004
	Nikola Nedovic , Vojin G. Oklobdzija, Dual-edge triggered storage elements and clocking strategy for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.577-590, May 2005
	Ashish Goel , Swarup Bhunia , Hamid Mahmoodi , Kaushik Roy, Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Antonio G. M. Strollo , Davide De Caro , Ettore Napoli , Nicola Petra, A novel high-speed sense-amplifier-based flip-flop, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1266-1274, November 2005
	Peiyi Zhao , Jason McNeely , Pradeep Golconda , Magdy A. Bayoumi , Robert A. Barcenas , Weidong Kuang, Low-power clock branch sharing double-edge triggered flip-flop, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.3, p.338-345, March 2007
	Martin Saint-Laurent , Baker Mohammad , Paul Bassett, A 65-nm pulsed latch with a single clocked transistor, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Chen Kong Teh , Mototsugu Hamada , Tetsuya Fujita , Hiroyuki Hara , Nobuyuki Ikumi , Yukihito Oowaki, Conditional data mapping flip-flops for low-power and high-performance systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.12, p.1379-1383, December 2006
	Jin-Fa Lin , Yin-Tsung Hwang , Ming-Hwa Sheu, Low Complexity Dual-Mode Pulse Generator Designs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.7, p.1812-1815, July 2008