Hard real-time scheduling for low-energy using stochastic data and DVS processors

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
	2	Burd, T., Pering, T., Stratakos, A., and Brodersen, W. A dynamic voltage scaled microprocessor system in IEEE Journal of Solid-State Circuits, No. 11, Vol. 35, November 2000, 1571-1580.
	3	A. Chandrakasan , V. Gutnik , T. Xanthopoulos, Data driven signal processing: an approach for energy efficient computing, Proceedings of the 1996 international symposium on Low power electronics and design, p.347-352, August 12-14, 1996, Monterey, California, United States
	4	Bharat P. Dave , Ganesh Lakshminarayana , Niraj K. Jha, COSYN: hardware-software co-synthesis of embedded systems, Proceedings of the 34th annual conference on Design automation, p.703-708, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266341]
	5	Gruian, F., and Kuchcinski, K. Low-energy directed architecture selection and task scheduling for system-level design in Proceedings of the 25th Euromicro Conference, 1999, pp. 296-302.
	6	Flavius Gruian , Krzysztof Kuchcinski, LEneS: task scheduling for low-energy systems using variable supply voltage processors, Proceedings of the 2001 conference on Asia South Pacific design automation, p.449-455, January 2001, Yokohama, Japan [doi>10.1145/370155.370511]
	7	Inki Hong , Miodrag Potkonjak , Mani B. Srivastava, On-line scheduling of hard real-time tasks on variable voltage processor, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.653-656, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289105]
	8	Tohru Ishihara , Hiroto Yasuura, Voltage scheduling problem for dynamically variable voltage processors, Proceedings of the 1998 international symposium on Low power electronics and design, p.197-202, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280894]
	9	Namyun Kim , Minsoo Ryu , Seongsoo Hong , M. Saksena , Chong-Ho Choi , Heonshik Shin, Visual assessment of a real-time system design: a case study on a CNC controller, Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), p.300, December 04-06, 1996
	10	Yann-Hang Lee , C. M. Krishna, Voltage-Clock Scaling for Low Energy Consumption in Real-Time Embedded Systems, Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications, p.272, December 13-15, 1999
	11	Seongsoo Lee , Takayasu Sakurai, Run-time voltage hopping for low-power real-time systems, Proceedings of the 37th conference on Design automation, p.806-809, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337785]
	12	Lehoczky, J., and Ramos-Thuel, S. An optimal algorithm for scheduling soft-aperiodic tasks in fixed-priority preemptive systems in Proceedings of RTSS'92, 110-123.
	13	Lehoczky, J., Sha, L., and Ding, Y. The rate monotonic scheduling algorithm: exact characterization and average case behavior in Proceedings of RTSS'89, 166-171.
	14	C. L. Liu , James W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM (JACM), v.20 n.1, p.46-61, Jan. 1973 [doi>10.1145/321738.321743]
	15	Locke, C.D., Vogel, D.R., and Mesler, T.J. Building a predictable avionics platform in Ada: a case study in Proceedings of RTSS'91, 181-189.
	16	Mosse, D., Aydin, H., Childers, B., and Melhem, R., Compiler-assisted dynamic power-aware scheduling for real-time applications. Worksop on Compilers and Operating Systems for Low-Power, October 2000.
	17	Massoud Pedram, Power optimization and management in embedded systems, Proceedings of the 2001 conference on Asia South Pacific design automation, p.239-244, January 2001, Yokohama, Japan [doi>10.1145/370155.370333]
	18	Trevor Pering , Tom Burd , Robert Brodersen, The simulation and evaluation of dynamic voltage scaling algorithms, Proceedings of the 1998 international symposium on Low power electronics and design, p.76-81, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280790]
	19	Trevor Pering , Thomas Burd , Robert Brodersen, Voltage scheduling in the IpARM microprocessor system, Proceedings of the 2000 international symposium on Low power electronics and design, p.96-101, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344530]
	20	Youngsoo Shin , Kiyoung Choi, Power conscious fixed priority scheduling for hard real-time systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.134-139, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309901]
	21	Dongkun Shin , Jihong Kim , Seongsoo Lee, Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications, IEEE Design & Test, v.18 n.2, p.20-30, March 2001 [doi>10.1109/54.914596]
	22	Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., Matsuda, K., Maeda, T., and Kuroda, T. A 300MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS, Proceedings of the ICC'97, 587-590.
	23	Weiser, M., Welch, B., Demers, A., and Shenker, S. Scheduling for reduced CPU energy in Proceedings of the First Symposium on Operating Systems Design and Implementation, November 1994.
	24	F. Yao , A. Demers , S. Shenker, A scheduling model for reduced CPU energy, Proceedings of the 36th Annual Symposium on Foundations of Computer Science (FOCS'95), p.374, October 23-25, 1995
	25	http://www.transmeta.com