L1 data cache decomposition for energy efficiency

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L1 data cache decomposition for energy efficiency

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 10 - 15

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Michael Huang	University of Illinois at Urbana-Champaign
Jose Renau	University of Illinois at Urbana-Champaign
Seung-Moon Yoo	University of Illinois at Urbana-Champaign
Josep Torrellas	University of Illinois at Urbana-Champaign

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 36, Citation Count: 27

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 27

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	Osman S. Unsal , Raksit Ashok , Israel Koren , C. Mani Krishna , Csaba Andras Moritz, Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.3, p.373-392, August 2003
	Jun Yang , Rajiv Gupta, Frequent value locality and its applications, ACM Transactions on Embedded Computing Systems (TECS), v.1 n.1, p.79-105, November 2002
	Hsien-Hsin S. Lee , Chinnakrishnan S. Ballapuram, Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Jun Yang , Youtao Zhang, Lightweight set buffer: low power data cache for multimedia application, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	S. Kim , N. Vijaykrishnan , M. Kandemir , M. J. Irwin, Energy-efficient instruction cache using page-based placement, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Jun Yang , Lan Gao , Youtao Zhang, Improving Memory Encryption Performance in Secure Processors, IEEE Transactions on Computers, v.54 n.5, p.630-640, May 2005
	Chuanjun Zhang , Frank Vahid , Jun Yang , Walid Najjar, A way-halting cache for low-energy high-performance systems, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Yan Luo , Jun Yang , Laxmi N. Bhuyan , Li Zhao, NePSim: A Network Processor Simulator with a Power Evaluation Framework, IEEE Micro, v.24 n.5, p.34-44, September 2004
	Ikhwan Lee , Yongseok Choi , Youngjin Cho , Yongsoo Joo , Hyeonmin Lim , Hyung Gyu Lee , Hojun Shim , Naehyuck Chang, Web-Based Energy Exploration Tool for Embedded Systems, IEEE Design & Test, v.21 n.6, p.572-586, November 2004
	Ben Juurlink , Pepijn de Langen, Dynamic techniques to reduce memory traffic in embedded systems, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
	Raksit Ashok , Saurabh Chheda , Csaba Andras Moritz, Coupling compiler-enabled and conventional memory accessing for energy efficiency, ACM Transactions on Computer Systems (TOCS), v.22 n.2, p.180-213, May 2004
	Zhichun Zhu , Xiaodong Zhang, Access-Mode Predictions for Low-Power Cache Design, IEEE Micro, v.22 n.2, p.58-71, March 2002
	Jaume Abella , Antonio González , Xavier Vera , Michael F. P. O'Boyle, IATAC: a smart predictor to turn-off L2 cache lines, ACM Transactions on Architecture and Code Optimization (TACO), v.2 n.1, p.55-77, March 2005
	Chuanjun Zhang , Frank Vahid , Jun Yang , Walid Najjar, A way-halting cache for low-energy high-performance systems, ACM Transactions on Architecture and Code Optimization (TACO), v.2 n.1, p.34-54, March 2005
	Chuanjun Zhang , Frank Vahid , Walid Najjar, A highly configurable cache architecture for embedded systems, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Jun Yang , Jia Yu , Youtao Zhang, A low energy cache design for multimedia applications exploiting set access locality, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.10-11, p.653-664, October/November 2005
	Raksit Ashok , Saurabh Chheda , Csaba Andras Moritz, Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency, ACM SIGOPS Operating Systems Review, v.36 n.5, December 2002
	Aristides Efthymiou , Jim D. Garside, An adaptive serial-parallel CAM architecture for low-power cache blocks, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Osman S. Unsal , Raksit Ashok , Israel Koren , C. Mani Krishna , Csaba Andras Moritz, Cool-cache for hot multimedia, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Daniel Gracia Perez , Gilles Mouchard , Olivier Temam, MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.43-54, December 04-08, 2004, Portland, Oregon
	Jaume Abella , Antonio González, Heterogeneous way-size cache, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Kyle Rupnow , Arun Rodrigues , Keith Underwood , Katherine Compton, Scientific applications vs. SPEC-FP: a comparison of program behavior, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Rajiv Ravindran , Michael Chu , Scott Mahlke, Compiler-managed partitioned data caches for low power, ACM SIGPLAN Notices, v.42 n.7, July 2007
	Chuanjun Zhang , Jun Yang , Frank Vahid, Low Static-Power Frequent-Value Data Caches, Proceedings of the conference on Design, automation and test in Europe, p.10214, February 16-20, 2004
	T. Venkata Kalyan , Madhu Mutyam, Word-interleaved cache: an energy efficient data cache architecture, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Hillery C. Hunter , Erik M. Nystrom , Daniel A. Connors , Wen-mei W. Hwu, Hardware-compiler co-design for adjustable data power savings, Microprocessors & Microsystems, v.33 n.4, p.244-253, June, 2009