Micro-operation cache

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Micro-operation cache: a power aware frontend for the variable instruction length ISA

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents

Huntington Beach, California, United States

Pages: 4 - 9

Year of Publication: 2001

ISBN:1-58113-371-5

Authors

Baruch Solomon	Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel
Avi Mendelson	Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel
Doron Orenstein	Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel
Yoav Almog	Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel
Ronny Ronen	Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Blac99	Bryan Black , Bohuslav Rychlik , John Paul Shen, The block-based trace cache, Proceedings of the 26th annual international symposium on Computer architecture, p.196-207, May 01-04, 1999, Atlanta, Georgia, United States
	Frie97	Daniel Holmes Friendly , Sanjay Jeram Patel , Yale N. Patt, Alternative fetch and issue policies for the trace cache fetch mechanism, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.24-33, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	Jour00	S. Jourdan, L. Rappoport, Y. Almog, M. Erez, A. Yoaz, R. Ronen, "eXtended Block Cache", in Proceedings of the International symposium on High Performance Computer Architecture, January 2000.
	Mann98	Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
	Pele94	A. Peleg and U. Weiser, "Dynamic Flow Instruction Cache Memory Organized around Trace Segments Independent of Virtual Address Line," U.S. Patent Number 5,381,533, Intel Corporation, 1994.
	Rote96	Eric Rotenberg , Steve Bennett , James E. Smith, Trace cache: a low latency approach to high bandwidth instruction fetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.24-35, December 02-04, 1996, Paris, France
	Upto00	Mike Upton, "The Intel Pentium 4 Processor", http://www.intel.com/pentium4, October 2000.

CITED BY 12

	Glenn Reinman , Brad Calder, Using a serial cache for energy efficient instruction fetching, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.11, p.675-685, November 2004
	Emil Talpes , Diana Marculescu, Impact of technology scaling on energy aware execution cache-based microarchitectures, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Roni Rosner , Micha Moffie , Yiannakis Sazeides , Ronny Ronen, Selecting long atomic traces for high coverage, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
	Emil Talpes , Diana Marculescu, Execution cache-based microarchitecture power-efficient superscalar processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.14-26, January 2005
	Kugan Vivekanandarajah , Thambipillai Srikanthan , Saurav Bhattacharyya, Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.373-379, January 27-30, 2004, Yokohama, Japan
	Chengmo Yang , Alex Orailoglu, Power-efficient instruction delivery through trace reuse, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Michael Behar , Avi Mendelson , Avinoam Kolodny, Trace cache sampling filter, ACM Transactions on Computer Systems (TOCS), v.25 n.1, p.3-es, February 2007
	Michele Co , Dee A. B. Weikle , Kevin Skadron, Evaluating trace cache energy efficiency, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.4, p.450-476, December 2006
	Oliverio J. Santana , Ayose Falcón , Alex Ramirez , Mateo Valero, Branch predictor guided instruction decoding, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Weiyu Tang , Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau, A predictive decode filter cache for reducing power consumption in embedded processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.2, p.14-es, April 2007
	Roni Rosner , Yoav Almog , Micha Moffie , Naftali Schwartz , Avi Mendelson, Power Awareness through Selective Dynamically Optimized Traces, ACM SIGARCH Computer Architecture News, v.32 n.2, p.162, March 2004
	Emil Talpes , Diana Marculescu, Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines, ACM SIGARCH Computer Architecture News, v.33 n.2, p.310-321, May 2005

INDEX TERMS

General Terms:
Design, Performance

Keywords:
instruction, instruction cache, micro-operation cache, power reduction

Collaborative Colleagues:

Baruch Solomon: colleagues

Avi Mendelson: colleagues

Doron Orenstein: colleagues

Yoav Almog: colleagues

Ronny Ronen: colleagues

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