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Cache memory performance in a unix enviroment
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Source ACM SIGARCH Computer Architecture News archive
Volume 14 ,  Issue 3  (June 1986) table of contents
Pages: 41 - 61  
Year of Publication: 1986
ISSN:0163-5964
Authors
Cedell Alexander  Texas Instruments
William Keshlear  Texas Instruments
Furrokh Cooper  Texas Instruments
Faye Briggs  Rice University
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 26,   Citation Count: 10
Additional Information:

cited by   index terms   collaborative colleagues  

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CITED BY  10
Richard Uhlig , David Nagle , Trevor Mudge , Stuart Sechrest , Joel Emer, Instruction fetching: coping with code bloat, ACM SIGARCH Computer Architecture News, v.23 n.2, p.345-356, May 1995
S. J. Eggers , R. H. Katz, Evaluating the performance of four snooping cache coherency protocols, ACM SIGARCH Computer Architecture News, v.17 n.3, p.2-15, June 1989
Anant Agarwal , John Hennessy , Mark Horowitz, Cache performance of operating system and multiprogramming workloads, ACM Transactions on Computer Systems (TOCS), v.6 n.4, p.393-431, Nov. 1988
Richard A. Uhlig , Trevor N. Mudge, Trace-driven memory simulation: a survey, ACM Computing Surveys (CSUR), v.29 n.2, p.128-170, June 1997
Håkon O. Bugge , Ernst H. Kristiansen , Bjørn O. Bakka, Trace-driven simulations for a two-level cache design in open bus systems, ACM SIGARCH Computer Architecture News, v.18 n.3a, p.250-259, June 1990
M. Freeman, An architectural perspective on a memory access controller, Proceedings of the 14th annual international symposium on Computer architecture, p.214-223, June 02-05, 1987, Pittsburgh, Pennsylvania, United States
S. J. Eggers , R. H. Katz, The effect of sharing on the cache and bus performance of parallel programs, ACM SIGARCH Computer Architecture News, v.17 n.2, p.257-270, April 1989
Robin W. Edenfield , Michael G. Gallup , William B. Ledbetter, Jr. , Ralph C. McGarity , Eric E. Quintana , Russel A. Reininger, The 68040 Processor. 2. Memory Design and Chip, IEEE Micro, v.10 n.3, p.22-35, May 1990
Mark D. Hill, A Case for Direct-Mapped Caches, Computer, v.21 n.12, p.25-40, December 1988
M. D. Hill , A. J. Smith, Evaluating Associativity in CPU Caches, IEEE Transactions on Computers, v.38 n.12, p.1612-1630, December 1989

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing
  B.8 Performance and Reliability

  D. Software
  D.4 OPERATING SYSTEMS
      D.4.0 General

          Nouns: UNIX


General Terms:
Algorithms, Design, Measurement, Performance, Theory

Collaborative Colleagues:
Cedell Alexander: colleagues
William Keshlear: colleagues
Furrokh Cooper: colleagues
Faye Briggs: colleagues

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