A microcoded RISC

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A microcoded RISC

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Source

ACM SIGARCH Computer Architecture News archive
Volume 14 , Issue 3 (June 1986) table of contents

Pages: 5 - 16

Year of Publication: 1986

ISSN:0163-5964

Authors

D. K. DuBose	Dept. of Electrical and Computer Eng., George Mason University, Fairfax, VA
D. K. Fotakis	Dept. of Electrical and Computer Eng., George Mason University, Fairfax, VA
D. Tabak	Dept. of Electrical and Computer Eng., George Mason University, Fairfax, VA

Publisher

ACM New York, NY, USA

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ABSTRACT

A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using the register window approach, is implemented. A bit-sliced (AMD2900) prototype is currently under construction.

CITED BY

Gautam B. Singh, GRIP: graphics reduced instruction processor, Proceedings of the 24th annual international symposium on Microarchitecture, p.143-152, September 1991, Albuquerque, New Mexico, Puerto Rico

INDEX TERMS

Primary Classification:
C. Computer Systems Organization
C.0 GENERAL
Subjects: Instruction set design (e.g., RISC, CISC, VLIW)