ACM Home Page
Please provide us with feedback. Feedback
Locality vs. criticality
Full text PdfPdf (961 KB)
Source International Symposium on Computer Architecture archive
Proceedings of the 28th annual international symposium on Computer architecture table of contents
Göteborg, Sweden
Pages: 132 - 143  
Year of Publication: 2001
ISBN:0-7695-1162-7
Also published in ...
Authors
Roy Dz-ching Ju  Microprocessor Research Labs, Intel Corporation
Alvin R. Lebeck  Department of Computer Science, Duke University
Chris Wilkerson  Microprocessor Research Labs, Intel Corporation
Editors
Srikanth T. Srinivasan  Department of Computer Science, Duke University
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\TCCA : TC on Computer Arhitecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 16,   Downloads (12 Months): 48,   Citation Count: 18
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/379240.379258
What is a DOI?

ABSTRACT

Current memory hierarchies exploit locality of references to reduce load latency and thereby improve processor performance. Locality based schemes aim at reducing the number of cache misses and tend to ignore the nature of misses. This leads to a potential mis-match between load latency requirements and latencies realized using a traditional memory system. To bridge this gap, we partition loads as critical and non-critical. A load that needs to complete early to prevent processor stalls is classified as critical, while a load that can tolerate a long latency is considered non-critical.

In this paper, we investigate if it is worth violating locality to exploit information on criticality to improve processor performance. We present a dynamic critical load classification scheme and show that 40% performance improvements are possible on average, if all critical loads are guaranteed to hit in the Ll cache. We then compare the two properties, locality and criticality, in the context of several cache organization and prefetching schemes. We find that the working set of critical loads is large, and hence practical cache organization schemes based on criticality are unable to reduce the critical load miss ratios enough to produce performance gains. Although criticality-based prefetching can help for some resource constrained programs, its benefit over locality-based prefetching is small and may not be worth the added complexity.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D. C. Burger, T. M. Austin, and S. Bennett. Evaluating Future Microprocessors-the SimpleScalar Tool Set. Technical Report 1308, Computer Sciences Department, University of Wisconsin-Madison, July 1996.
2
 
3
 
4
5
6
 
7
8
 
9
10
 
11
12
13
14
 
15
J. A. Rivers and E. S. Davidson. Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. In Proceedings of the 1996 International Conference on Parallel Processing, volume 1, pages 154-163, August 1996.
16
17
 
18
 
19
 
20
21

CITED BY  18

Collaborative Colleagues:
Roy Dz-ching Ju: colleagues
Alvin R. Lebeck: colleagues
Chris Wilkerson: colleagues
Srikanth T. Srinivasan: colleagues