| LES: a layout expert system |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 672 - 678
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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Y.-L. S. Lin
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Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
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D. D. Gajski
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Dept. of Information and Computer Science, University of California at Irvine, Irvine, CA
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Downloads (6 Weeks): 6, Downloads (12 Months): 7, Citation Count: 4
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ABSTRACT
In this paper we describe an expert system for layout generation in a hierarchical VLSI design system. It applies a combination of rule- and algorithmic-based techniques on a new layout style. Experimental results have demonstrated the superiority of this expert system against various standard-cell systems and its competitiveness with human designers.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Fle75
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Fleisher, H. and L. I. Maissel, "An Introduction to Array Logic," IBM J. of Res. and Dev., vol. 19, no. 2, pp. 98-109, Mar. 1975.
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For85
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Forgy, C. L., "The OPS83 User's Manual and Report," Production Systems Technologies, Inc., Pittsburgh, PA, Mar. 1985.
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Kes85
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Kessler, A. J. and A. Ganesan, "Standard Cell VLS{ Design: A Tutorial," {EEE Circuits and Devices Magazine, voI. 1, no. 1, pp. 17-33, Jan. 1985.
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Kim84
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Kim, J. H., J. McDermott and D. P. Siewiorek, "Exploiting Domain Kaowledge in IC Cell Layout," IEEE Design ~ Test Magazine, vol. 1, no. 3, pp. 52-64, Aug. 1984.
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Kol85
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Kollaritsch, P. W. and N. H. Weste, "TOPOLO- GIZER" An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout," {EEE J. of Solid-State Circuits, vol. SC-20, no. 3, pp 799-804, Jun. 1985.
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Lin86
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Lin, Y-L. S., "A Knowledge-Based Approach to Layout Automation Problem," Ph. D. Dissertation Proposal, Dept. of Computer Science, Univ. o~ Ill., Urbana. Ill., Jan. 1986.
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Lop80
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Lopes, A. and H. Law~ "A Dense Gate Matrix Layout Method for MOS VLSI," IEEE Trans. on Electronic Devices, vol. ED-27, no. 81 pp. 1671-1675, Aug. 1980.
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Mea80
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Nii86
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Wei67
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Weinberger, A., "Large Scale Integration of MOS Complex Logic: A Layout Method," {EEE J. of Solid-State Circuits, vol. SC-2, no. 4, pp. 182-190, Dec. 1967.
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Wes81
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Weste, N., "MULGA -- An Interactive Symbolic Layout System for the Design of Integrated Circuits," The Bell System Tech. jr., vol. 60, no. 6., part 1, pp. 823-857, Jul.-Aug. 1981.
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CITED BY 4
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C.-L. Ong , J.-T. Li , C.-Y. Lo, GENAC: an automatic cell synthesis tool, Proceedings of the 26th ACM/IEEE conference on Design automation, p.239-244, June 25-28, 1989, Las Vegas, Nevada, United States
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Knut M. Just , Edgar Auer , Werner L. Schiele , Alexander Schwaferts, PALACE: a layout generator for SCVS logic blocks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.468-473, June 24-27, 1990, Orlando, Florida, United States
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