ACM Home Page
Please provide us with feedback. Feedback
LES: a layout expert system
Full text PdfPdf (1.06 MB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 672 - 678  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
Y.-L. S. Lin  Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
D. D. Gajski  Dept. of Information and Computer Science, University of California at Irvine, Irvine, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 7,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/37888.37996
What is a DOI?

ABSTRACT

In this paper we describe an expert system for layout generation in a hierarchical VLSI design system. It applies a combination of rule- and algorithmic-based techniques on a new layout style. Experimental results have demonstrated the superiority of this expert system against various standard-cell systems and its competitiveness with human designers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
Fle75
Fleisher, H. and L. I. Maissel, "An Introduction to Array Logic," IBM J. of Res. and Dev., vol. 19, no. 2, pp. 98-109, Mar. 1975.
 
For85
Forgy, C. L., "The OPS83 User's Manual and Report," Production Systems Technologies, Inc., Pittsburgh, PA, Mar. 1985.
 
Kes85
Kessler, A. J. and A. Ganesan, "Standard Cell VLS{ Design: A Tutorial," {EEE Circuits and Devices Magazine, voI. 1, no. 1, pp. 17-33, Jan. 1985.
 
Kim84
Kim, J. H., J. McDermott and D. P. Siewiorek, "Exploiting Domain Kaowledge in IC Cell Layout," IEEE Design ~ Test Magazine, vol. 1, no. 3, pp. 52-64, Aug. 1984.
 
Kol85
Kollaritsch, P. W. and N. H. Weste, "TOPOLO- GIZER" An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout," {EEE J. of Solid-State Circuits, vol. SC-20, no. 3, pp 799-804, Jun. 1985.
 
Lin86
Lin, Y-L. S., "A Knowledge-Based Approach to Layout Automation Problem," Ph. D. Dissertation Proposal, Dept. of Computer Science, Univ. o~ Ill., Urbana. Ill., Jan. 1986.
 
Lop80
Lopes, A. and H. Law~ "A Dense Gate Matrix Layout Method for MOS VLSI," IEEE Trans. on Electronic Devices, vol. ED-27, no. 81 pp. 1671-1675, Aug. 1980.
 
Mea80
 
Nii86
 
Wei67
Weinberger, A., "Large Scale Integration of MOS Complex Logic: A Layout Method," {EEE J. of Solid-State Circuits, vol. SC-2, no. 4, pp. 182-190, Dec. 1967.
 
Wes81
Weste, N., "MULGA -- An Interactive Symbolic Layout System for the Design of Integrated Circuits," The Bell System Tech. jr., vol. 60, no. 6., part 1, pp. 823-857, Jul.-Aug. 1981.


Collaborative Colleagues:
Y.-L. S. Lin: colleagues
D. D. Gajski: colleagues