ACM Home Page
Please provide us with feedback. Feedback
Hierarchical design based on a calculus of nets
Full text PdfPdf (468 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 649 - 653  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
B. Becker  Fachbereich 10, Universität des Saarlandes, D-6600 Saarbrücken, FRG
G. Hotz  Fachbereich 10, Universität des Saarlandes, D-6600 Saarbrücken, FRG
R. Kolla  Fachbereich 10, Universität des Saarlandes, D-6600 Saarbrücken, FRG
P. Molitor  Fachbereich 10, Universität des Saarlandes, D-6600 Saarbrücken, FRG
H.-G. Osthof  Fachbereich 10, Universität des Saarlandes, D-6600 Saarbrücken, FRG
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 12,   Citation Count: 6
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/37888.37992
What is a DOI?

ABSTRACT

We present an algebraic approach to hierarchical design of integrated circuits. This approach is based on a “calculus of nets” which includes topological as well as behavioural aspects of integrated circuits. We have developed a hierarchical design system called CADIC which is build around this calculus in much the same way as e.g. Algol is build around numerics. An example for the design of a family of fast adders will demonstrate the power of this calculus. Finally we will give a summary outline on the structure of procedures which automatically transform the design into lower design levels.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
L.Cardelli: "An Algebraic Approach to Hardware Description and Verification~ PH.D. Thesis, Edinburgh 1082.
 
2
E.Clarke, Y.Feng: "ESCHER- A geometrical Layout System for Recursively Defined Circuits" CMU-CS-85-150, Department of Computer Science, Carnegie-Mellon University, Pitsburgh 1985.
 
3
E.H~rbst, M.Nett, H.Schw~rtzel: "VENUS - Entwurf yon VLSI'Schaltungen" Springer-Verlag Berlin Heidelberg New-York Tokyo 1986.
 
4
G.Hotz: "Eine Algebraisierung des Syntheseproblems fiir Schaltkreise" EIK 1, 1965, pp.185-205,209-231.
 
5
G.Hotz, B.Becker, R.Kolla, P.Molitor: "Ein logisch-topologischer Kalkiil zur Konstruktion yon integrierten Schaltkreisen" Informatik: Forschung mad Entwicklung, Heft 1 und 2, Springer Verlag 1986.
 
6
C.D.Kloos: "Towards a Formalization of Digital Circuit Design" TUM-I8604, February 1986, Technische Universitiit M~inchen.
 
7
R.Kolla: "Spezifikation und Expansion logisch-topotogischer Netze" Dissertation, Sa~rbriicken 1086/87.
 
8
R.Kolla "Verification of logic-topological Nets" will appear as technical report, SFB124, Saarbriicken 1987.
 
9
C.E.Leiserson, R.Y.Pinter: "Optimal placement for fiver routing" SAM J. Comput. 12, pp.447-462, 1983.
 
10
T.Lengauer, K.Mehlhora: "The HILL-System: A Design Environment for the Hierarchical Specification, Compaction and Simulation of Integrated Circuit Layouts" MIT VLSI Conference 1984, pp.139-149, Artech House.
 
11
P.Molitor: "Layer Assignment by Simulated Annealing" Microprocessing and Microprogramming 16 (1985), pp.345-350, North-Holland.
 
12
P.Molitor: "Uber die Bikategorie der logisch- topologischen Netze und i hre Semantik" Dissertation, Saarbriicken 1986.
 
13
 
14
P.Molitor: "Free Net Algebras in VLSI-Theory"" in preparation.
 
15
P.Molitor, R.Kolla: "A note on hierarchical layer-assignment" Tit 8/86, SFB124, Saarbriicken 1986.
 
16
R.Y.Pinter: "Optimal layer assignment for interconnect" ICCC 1982, pp.398-401.
 
17
M.Sheeran: "gFP- An algebraic VLSI design language" PH.D. Thesis, University of Oxford, England 1984.
 
18
J. Sklansky "Conditional-sum addition logic" IRE-EC 9, 226-231 (1960)


Collaborative Colleagues:
B. Becker: colleagues
G. Hotz: colleagues
R. Kolla: colleagues
P. Molitor: colleagues
H.-G. Osthof: colleagues