Statistics for parallelism and abstraction level in digital simulation

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Statistics for parallelism and abstraction level in digital simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents

Miami Beach, Florida, United States

Pages: 588 - 591

Year of Publication: 1987

ISBN:0-8186-0781-5

Authors

L. Soule	Stanford University, Center for Integrated Systems
R. Blank	Stanford University, Center for Integrated Systems

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 12

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents statistics of several designs at four design abstraction levels - the instruction, behavioral, RTL, and gate levels. The data includes simulation time profiles, maximum speedup and limitations of parallelism, typical model evaluation times, event distributions, element intensities, and component counts for the four abstraction levels. This data is then used to analyze and evaluate several speed-up approaches: mixed-level simulation, parallel software simulators, parallel pipelined hardware accelerators, and decreased time resolution. The results show that element activity is around 0.1 to 0.5% at any particular time point. For the example circuits (3400 gates, 5000 gates, and 150,000 transistors), simulations show that parallelism can obtain speed-ups between 10-30. We found a factor of roughly ten speed-up between each of the abstraction levels.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Paul Chow, Personal communicaUon.
	2	Tom Blank, "A Survey of Hardware Accelerators Used in Computer-Aided Design", IEEE Transactions on Design and Test, August, 1984, pp. 21-39.
	3	Edward H. Frank, Exploiting parallelism in a switch-level simulation machine, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.20-26, July 1986, Las Vegas, Nevada, United States
	4	K. F. Wong , M. A. Franklin , R. D. Chamberlain , B. L. Shing, Statistics on logic simulation, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.13-19, July 1986, Las Vegas, Nevada, United States
	5	Lightner, Moceyunas, "CSIM: The Evorution of a Behavioral Level Simulator from a Functional Simulator: Implementation Issues and Performance Measurements", ICCAD.85, IEEE, November 1985, pp. 350-352.
	6	David R. Jefferson, Virtual time, ACM Transactions on Programming Languages and Systems (TOPLAS), v.7 n.3, p.404-425, July 1985 [doi>10.1145/3916.3988]

CITED BY 12

	Larry Soulé , Tom Blank, Parallel logic simulation on general purpose machines, Proceedings of the 25th ACM/IEEE conference on Design automation, p.166-171, June 12-15, 1988, Atlantic City, New Jersey, United States
	Larry Soulé , Anoop Gupta, An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation, ACM Transactions on Modeling and Computer Simulation (TOMACS), v.1 n.4, p.308-347, Oct. 1991
	Vishwani D. Agrawal , Srimat T. Chakradhar, Performance estimation in a massively parallel system, Proceedings of the 1990 conference on Supercomputing, p.306-313, October 1990, New York, New York, United States
	David B. Bernstein , Werner van Almsick , Wilfried Daehn, Distributed simulation for structural VHDL netlists, Proceedings of the conference on European design automation, p.598-603, September 19-23, 1994, Grenoble, France
	K. Subramanian , M. R. Zargham, Distributed and parallel demand driven logic simulation, Proceedings of the 27th ACM/IEEE conference on Design automation, p.485-490, June 24-27, 1990, Orlando, Florida, United States
	L. Soule , A. Gupta, Characterization of parallelism and deadlocks in distributed digital logic simulation, Proceedings of the 26th ACM/IEEE conference on Design automation, p.81-86, June 25-28, 1989, Las Vegas, Nevada, United States
	Mary L. Bailey , Jack V. Briner, Jr. , Roger D. Chamberlain, Parallel logic simulation of VLSI systems, ACM Computing Surveys (CSUR), v.26 n.3, p.255-294, Sept. 1994
	Giovanni De Micheli , David C. Ku, HERCULES—a system for high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.483-488, June 12-15, 1988, Atlantic City, New Jersey, United States
	Dale E. Martin , Radharamanan Radhakrishnan , Dhananjai M. Rao , Malolan Chetlur , Krishnan Subramani , Philip A. Wilsey, Analysis and simulation of mixed-technology VLSI Systems, Journal of Parallel and Distributed Computing, v.62 n.3, p.468-493, March 2002
	Larry Soule , Anoop Gupta, Parallel Distributed-Time Logic Simulation, IEEE Design & Test, v.6 n.6, p.32-48, November 1989
	A. Bataineh , F. Özgüner, Parallel-and-vector implementation of the event-driven logic simulation algorithm on the Cray Y-MP supercomputer, Proceedings of the 1992 ACM/IEEE conference on Supercomputing, p.444-452, November 16-20, 1992, Minneapolis, Minnesota, United States
	V. D. Agrawal , S. T. Chakradhar, Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems, IEEE Transactions on Parallel and Distributed Systems, v.3 n.6, p.739-746, November 1992