| RED: resistance extraction for digital simulation |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 570 - 573
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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D. Stark
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Center for Integrated Systems, Stanford University, Stanford, CA
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M. Horowitz
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Center for Integrated Systems, Stanford University, Stanford, CA
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Downloads (6 Weeks): 4, Downloads (12 Months): 10, Citation Count: 2
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ABSTRACT
This paper describes an extractor designed to produce resistance values for use in digital circuit simulation. REDS avoids resistance extraction on most nets in a design using a simple filter based on the perimeter and area values calculated by the capacitance extractor, allowing it to concentrate on areas where resistance may substantially affect circuit timing. Nets are extracted using a fast square counting algorithm, and simplified before output to remove spurious elements. REDS is designed to work on the Magic layout database.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. D. Bastian , M. Ellement , P. J. Fowler , C. E. Huang , L. P. McNamee, Symbolic Parasitic Extractor for Circuit Simulation (SPECS), Proceedings of the 20th conference on Design automation, p.346-352, June 27-29, 1983, Miami Beach, Florida, United States
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D.T. Fitzpattrick, UMEXTRA: A Manhttan Circuit Extractor', Electronic Research Lab. Memo M82/42, Electronics Research Laboratory, University of California, Berkeley, January, 1982.
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Mark Horowitz et sl., "A 32b Microprocessor with On-Chip 2K Byte Instruction Cache", 1987 International Solid .State Circuits ConJercncc Digest of Technical Papers, 30-31,328.
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Mark Horowitz gad Robert W. Dutton, 'Resistance Extraction from Mask Layout Data", IEEE Transactions on Computer Aided Design, Vol. Cad*2, No. 3, July 1983, 145-150.
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Shojiro Marl and James A. Wilmore, UResistance Extraction in a Hierarchical IC Artwork Verification System", Digest of Technical Papers, IEEE International Conference on Computer Aided Design, 1985 196-198.
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3orge B.ubenstein, P~ut Peufield, Jr. aad Mark A. Horowitz, "Signal Delay in RC Tree Networks',IEEE Transactions on Computer Aided Design, Vol. Cad-2, No. 3, July 1983, 202-210.
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