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Layout optimization of CMOS functional cells
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 544 - 551  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
R. L. Maiasz
J. P. Hayes
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 7
Additional Information:

abstract   cited by   index terms   collaborative colleagues  

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ABSTRACT

An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and van Cleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.


CITED BY  7
Robert L. Maziasz , John P. Hayes, Exact width and height minimization of CMOS cells, Proceedings of the 28th conference on ACM/IEEE design automation, p.487-493, June 17-22, 1991, San Francisco, California, United States
C.-L. Ong , J.-T. Li , C.-Y. Lo, GENAC: an automatic cell synthesis tool, Proceedings of the 26th ACM/IEEE conference on Design automation, p.239-244, June 25-28, 1989, Las Vegas, Nevada, United States
S. Rao Kosaraju, Euler paths in series parallel graphs, Proceedings of the thirty-third annual ACM symposium on Theory of computing, p.237-240, July 2001, Hersonissos, Greece
C. C. Chen , S.-L. Chow, The layout synthesizer: an automatic Netlist-to-Layout system, Proceedings of the 26th ACM/IEEE conference on Design automation, p.232-238, June 25-28, 1989, Las Vegas, Nevada, United States
Yung-Ching Hsieh , Chi-Yi Hwang , Youn-Long Lin , Yu-Chin Hsu, LiB: a cell layout generator, Proceedings of the 27th ACM/IEEE conference on Design automation, p.474-479, June 24-27, 1990, Orlando, Florida, United States
Martin Lefebvre , Chong Chan , Grant Martin, Transistor placement and interconnect algorithms for leaf cell synthesis, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
Hamidreza Hashempour , Fabrizio Lombardi, Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France

INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies
      B.7.2 Design Aids
          Subjects: Layout


General Terms:
Design

Collaborative Colleagues:
R. L. Maiasz: colleagues
J. P. Hayes: colleagues

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