| A dynamic and efficient representation of building-block layout |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 376 - 384
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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W.-M. Dai
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Department of Electrical Engineering and Computer Sciences, and the Electronics Research Laboratory, University of California, Berkeley, CA
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M. Sato
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Department of Electrical Engineering and Computer Sciences, and the Electronics Research Laboratory, University of California, Berkeley, CA
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E. S. Kuh
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Department of Electrical Engineering and Computer Sciences, and the Electronics Research Laboratory, University of California, Berkeley, CA
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Downloads (6 Weeks): 0, Downloads (12 Months): 14, Citation Count: 7
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ABSTRACT
Dynamic layout representation is a key problem in developing a building block layout system. We have unified topological and geometrical representations, and developed efficient methods to update topological information after geometrical operations. The experimental results are very promising. This representation is the key for information flow in BEAR — a new building block layout system being developed at U. C. Berkeley.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Sheldon B. Akers , James M. Geyer , Donald L. Roberts, IC mask layout with a single conductor layer, Proceedings of the 7th workshop on Design automation, p.7-16, June 22-25, 1970, San Francisco, California, United States
[doi> 10.1145/800160.805107]
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2
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K.D. Brinkmann and D. A. Mlynski, "Computer aided chip minimization for IC-layout," in Proc. of Int. Syrup. on Circuits and Systems, pp. 650-653, 1976.
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3
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R.L. Brooks, C. A. B. Smith, A. H. Stone, and W. T. Tutte, "The dissection of rectangles into squares," Duke Math. J., Vol. 7, pp. 312-340, 1940.
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4
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N.P. Chen, C. P. Hsu, and E. S. Kuh, "The Berkeley building-block (BBL) layout system for VLSI design," in Dig. Tech. Papers, IEEE Int. Conf. on Computer-Aided Des~'gn, pp. 40-41, 1983.
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5
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B.W. Colbry and J. Soukup, "Layout aspects of the VLSI microprocessor design," in Proc. of I98g IEEE Int. Syrup. on Circuits and Systems, pp. 1214-1228, 1982.
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6
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W.M. Dai, T. Asano, E. S. Kuh, "Routing region definition and ordering scheme for building-block layout," IEEE Trans. on Computer- Aided Design of ICs and Syat., Vol. CAD-4, No. 3, 1985.
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7
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W.M. Dad and E. S. Kuh, "Global spacing of building-block layout," to appear in Proc. of VLSI 1987, 1987.
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8
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K. Kani, H. Kawanishi, and A. Kishirnoto, "ROBIN: A building block LSI routing program," in Pros. of Int. Syrup. on Circuits and Systems, pp. 658-660, 1976.
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9
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E.S. Kuh, Ed., "The special issue on routing and microelectronics," IEEE Trans. on Computer-Aided Design of ICa and Syst., Vol. CAD-2, No. 4, Oct. 1983.
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10
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11
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U.P. Lauther, "Channel routing in a general cell environment," in Proc. of VLS{1985, 1985.
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12
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T. Ohtsuki, N. Sugiyama, and H. Kawanishi, "An optimization technique for integrated circuit layout design," in Proc. ICCST-Kyoto, pp. 67-68, Sept. t970.
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13
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14
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R.H.J.M. Otten, "Complexity and diversity in IC layout design," in Pros. of Int. Conf. on Circuits and Computers, pp. 764-767, 1980.
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15
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R. H. $. M. Otten, Layout Structures, IBM Research Report RC9657~ Thomas $. Watson Research Center, Yorktown Heights, N. Y., 1982.
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16
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J.K. Ousterhout, "Corner Stitching: A Data, Structuring Technique for VLSI Layout Tools," IEEE Trans. on Computer-Aided Design of IC~ and S~at., Vol. CAD-3, No. 1, 1984.
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17
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G. Persky , C. Enger , D. M. Selove, The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing, Proceedings of the 18th conference on Design automation, p.22-28, June 29-July 01, 1981, Nashville, Tennessee, United States
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18
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19
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B. T. Preas and C. S. Chow, "Placement and routing algorithms for topological integrated circuit layout," in Proe. of Int. Syrup. on Circuita and Syatems, pp. 17-20, 1985.
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20
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21
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22
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M. Wiesel and D. A. Mlynski, "An efficient channel model for building block LSI," in Proc. of Int. Syrup. on Circuits and Systems, pp. 118-121, 1981.
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23
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K. Zibert and R. Sa~i, "On computer aided hybrid circuit layout," in Proc. Int. Syrup. on Circuits and Systems, pp. 314-318, 1974.
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CITED BY 7
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Christian Masson , Remy Escassut , Denis Barbier , Daniel Winer , Gregory Chevallier, Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system, Proceedings of the 28th conference on ACM/IEEE design automation, p.259-264, June 17-22, 1991, San Francisco, California, United States
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Le-Chin Eugene Liu , Hsiao-Ping Tseng , Carl Sechen, Chip-level area routing, Proceedings of the 1998 international symposium on Physical design, p.197-204, April 06-08, 1998, Monterey, California, United States
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Christian Masson , Denis Barbier , Remy Escassut , Daniel Winer , Gregory Chevallier , Pierre François Zeegers, CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
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Keishi Sakanushi , Shigetoshi Nakatake , Yoji Kajitani, The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.267-274, November 08-12, 1998, San Jose, California, United States
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