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The ALGIC silicon compiler system: implementation, design experience and results
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 370 - 375  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
J. Schuck  Technical University of Darmstadt, Institut fuer Halbleitertechnik, Schlossgartenstr.8, D-6100 Darmstadt, FR Germany
N. Wehn  Technical University of Darmstadt, Institut fuer Halbleitertechnik, Schlossgartenstr.8, D-6100 Darmstadt, FR Germany
M Glesner  Technical University of Darmstadt, Institut fuer Halbleitertechnik, Schlossgartenstr.8, D-6100 Darmstadt, FR Germany
G. Kamp  Technical University of Darmstadt, Institut fuer Halbleitertechnik, Schlossgartenstr.8, D-6100 Darmstadt, FR Germany
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom design style. Main components of the ALGIC system are a system monitor module, a parameterisable macrocell generator, an appropriate floorplanner with 100% routing solution including planar VDD/GND trees and a block-oriented timing verifier. One essential feature of the system is the high degree of integration between all program modules using the concept of abstract data types. The flexibility and performance of the whole system is demonstrated by real design examples in the field of DSP applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D.E.Thomas et. al : "Automatic Data Path Synthesis", I~ Cunputer, Decanber 1983, pp. 59-70
 
2
R.Jamier, A.A.Jerraya: "Appollon, A Data Path Compiler", Proc. ICCD 86 conference, Port Chester, Oct. 85
 
3
Siskind, Southard, Crouch: "Generating Custom High-Performance VLSI Designs from Succinct Algorithmic Descriptions", Proc. Cnuf. on Advanced Research in VIZI, KrT, Jan. 82
 
4
 
5
J2LRabaey, S.P.Pope, R.W.Brodersen- "An Integrated Autunated Layout Generation ~'ste~ for DSP circuits", IEEE transactions on Computer Aided Design, VoI.CAD-4. ,ND.3,1985, pp.285-296
 
6
P.B.Denyer, A.F.Murray, D.Renshaw: "FIRST: Prospect and Retrospect", IEEE Workshop on VLSI Signal Processing, Los Angelos, ~ov. 1984, pp. 252-263
 
7
N.Glesner, J.Schuck, H.Jo~pen: "A Flexible Silicon Coapiler for Digital Signal Processing Circuits", Proc. of ICCD 34-Conf., Port Chester, N.Y., Oct.84, pp. 845-850
 
8
J.Schuck, M.Glesner, H.Joepen: "ALGIC - A Flexible Silicon Co~pi!er for Digital Signal Processing" IEEE Press, VIZI Signal Processing, 1984, pp. 216-227
 
9
J. Schuck, M.Glesner, M. Lackner: "First Results and Design EA~rience w~/th the Silicon Cc~piler System ALGIC", IEEE Press, VLSI Signal Processing, 1986, pp.32-43
 
10
G. Sch~er: "Intermediate Form of SELLAV' Second Technical Report, CVT Project, TH Darmstadt 1983
 
11
H.Joepen, H.Glesner: "Architecture Construction for a General Silicon Canpiler System", Proc. of ICCD 85-Conf., Port Chester, N.Y., Oct.85, pp. 312-316
 
12
H.Joepen, M.Glesner: "OptL~%l Structuring of Hierarchical Control-Pathes in a Silicon Compiler b"yst~n", Proc. of ICCAD 86 Conf., Santa Clara, Nov.86
 
13
N.Glesner, H.Joepen, J.Schuck, N.Wehn: "Silicon Campilation from HDL and S~iliar sources", published in '~{ardware description languages" by North Holland, Volume 7, Sumner 1986
 
14
J.$chuck, ~4.Glesner: "Layout Generation for Multipliers in VLSI-Digital Signal Processing", ESSCIRC, Sept.84, Ed/~gh, pp.165-170
 
15
N.Wehn: "HOPPIA- A Floorplanner for Hierachieal Hacrocell Design' Internal Report, TH Darmstadt, Institut fuer Halbleitertechnik, Feb.86
 
16
 
17
S.Meier: "Architectural Studies for the Realization of Integrated DSP Circuits", Diplamarbeit, TH Darmstadt, Institut fuer Halbleiterte~k, Jan. 86
 
18
T.Noll: "Seni-Systolic Maximum Rate Transversal Filters With Pr~amm~le Coefficients" Systolic Array, edited by Will Moore et al., Published by Adam Hilger, Bristol 1987, pp. 103-112
 
19
W. Ulbricht, T. Noll: "Design of dedicated MOS Digital Filters for high-speed applications" Proc. of internaticn Symposi~n on Circuits and Systa~s, Tokio 1985, pp. 255-258


Collaborative Colleagues:
J. Schuck: colleagues
N. Wehn: colleagues
M Glesner: colleagues
G. Kamp: colleagues