| Strip layout: a new layout methodology for standard circuit modules |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 363 - 369
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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J. Apte
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Computer Science Department, Duke University, Durham, North Carolina
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G. Kedem
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Computer Science Department, Duke University, Durham, North Carolina
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Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 0
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ABSTRACT
In this paper we describe Strip Layout, a new layout methodology that is suitable for automatically laying out standard circuit modules and for automatic module generation from transistor net-list. We demonstrate that the new layout methodology yields circuits that are denser than standard cell layout while retaining all the advantages of standard cells. Moreover, Strip Layout could be generated by simple algorithms at high speed.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. Kedem and K. Kozminski, "A Standard Cell Based Silicon Compiler", IEEE 1986 Custom Integrated Circuit Conference. pp 120-124.
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Rose, J.E.,G. Kedem, W. Krakow, K. Kozminskim "VPNR Tool Developers Guide", Unpublished Manuscript.
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Suaris, P.R., Kedem, G., "Standard Cell Placement by Quadrasection", Unpublished Manuscript.
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Vivek Krishna De, "A Heuristic Global Router", MS thesis Department of Electrical Engineering, Duke University, July 1986. Computer Science Department, Duke University, Tech Report CS-1986-31.
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Sechen, C.~ Sangiovanni-~incentelli A., "The TimberWolf Placement and Routing Package", IEEE Journal of Solid-state Circuits, vol. SC-20, no. 2, April 1985~ pp. 510- 522
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T. Uehara and W.M. van Cleemput, "Optimal Layout of CMOS Functional Arrays" IEEE Trans. on Comp. Vol. C30, No. 5, May 1981, pp. 305'311.
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