Accelerated transition fault simulation

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Accelerated transition fault simulation

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents

Miami Beach, Florida, United States

Pages: 237 - 243

Year of Publication: 1987

ISBN:0-8186-0781-5

Authors

M. H. Schultz
F. Brglez

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 12

Additional Information:

abstract cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. An experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. Tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in CMOS.

CITED BY 12

	C. T. Glover , M. R. Mercer, A deterministic approach to adjacency testing for delay faults, Proceedings of the 26th ACM/IEEE conference on Design automation, p.351-356, June 25-28, 1989, Las Vegas, Nevada, United States
	M. Schulz , F. Fink , K. Fuchs, Parallel pattern fault simulation of path delay faults, Proceedings of the 26th ACM/IEEE conference on Design automation, p.357-363, June 25-28, 1989, Las Vegas, Nevada, United States
	Weiwei Mao , Michael D. Ciletti, Correlation-reduced scan-path design to improve delay fault coverage, Proceedings of the 28th conference on ACM/IEEE design automation, p.73-79, June 17-22, 1991, San Francisco, California, United States
	Ankan K. Pramanick , Sudhakar M. Reddy, On the fault coverage of delay fault detecting tests, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Clay S. Gloster Jr. , Franc Brglez, Boundary Scan with Built-In Self-Test, IEEE Design & Test, v.6 n.1, p.36-44, January 1989
	F. Fink , K. Fuchs , M. H. Schulz, Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns, IEEE Transactions on Computers, v.41 n.12, p.1527-1536, December 1992
	Xiao Liu , Michael S. Hsiao , Sreejit Chakravarty , Paul J. Thadikaran, Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors, Journal of Electronic Testing: Theory and Applications, v.19 n.4, p.437-445, August 2003
	Benoit Nadeau-Dostie , Dwayne Burek , Abu S. M. Hassan, ScanBist: A Multifrequency Scan-Based BIST Method, IEEE Design & Test, v.11 n.1, p.7-17, January 1994
	Stelios Neophytou , Maria K. Michael , Spyros Tragoudas, Test set enhancement for quality transition faults using function-based methods, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Ali Chehab , Saurabh Patel , Rafic Makki, Scaling of iDDT Test Methods for Random Logic Circuits, Journal of Electronic Testing: Theory and Applications, v.22 n.1, p.11-22, February 2006
	Frank Pöhl , Walter Anheier, Quality Determination for Gate Delay Fault Tests Considering Three-State Elements, Journal of Electronic Testing: Theory and Applications, v.14 n.1-2, p.49-55, Feb./April 1999
	P. Cavallera , P. Girard , C. Landrault , S. Pravossoudovitch, DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits, Proceedings of the 1996 European conference on Design and Test, p.79, March 11-14, 1996