A practical moat router

ABSTRACT

The final step in the layout of integrated circuits involves connecting a central module to a surrounding ring of pads. Hence the region to be routed is in the shape of a moat. This paper presents a practical approach to the moat routing problem. The approach is based on an efficient channel routing algorithm with additional features addressing the characteristics of the moat configuration. While signal nets are similar to those of a channel router, power nets are routed in a single layer of metal. The geometry of the moat imposes some restrictions, but often allows additional compaction of the routes. Each side of the moat requires a different amount of space to complete the routing, and each side of the pad ring may be moved independently. This produces an asymmetrical moat, which minimizes chip area and guarantees 100 percent routing completion.

REFERENCES

• 1: Smith, Lyle R., et. al., "A New Area Router, the LRS Algorithm," IEEE ICCC '82, (Sept.-Oct. 1982), pp. 256-259.
• 2: Takeshi Yoshimura, An efficient channel router, Proceedings of the 21st conference on Design automation, p.38-44, June 25-27, 1984, Albuquerque, New Mexico, United States
• 3: LaPaugh, Andrea S., "A Polynomial Time Algorithm for Optimal Routing Around a Rectangle," Proc. 21st Annual IEEE Symposium on Foundations of Computer Science, October 1980, pp. 282-293.
• 4: M. Wiesel , D. A. Mlynski, Two-dimensional channel routing and channel intersection problems, Proceedings of the 19th conference on Design automation, p.733-739, January 1982

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Design