| Geometrical compaction in one dimension for channel routing |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 140 - 145
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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J. Royle
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SDA Systems Inc., 555 River Oaks Parkway, San Jose, California
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M. Palczewski
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SDA Systems Inc., 555 River Oaks Parkway, San Jose, California
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H. VerHeyen
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SDA Systems Inc., 555 River Oaks Parkway, San Jose, California
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N. Naccache
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SDA Systems Inc., 555 River Oaks Parkway, San Jose, California
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J. Soukup
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SDA Systems Inc., 555 River Oaks Parkway, San Jose, California
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| Bibliometrics |
Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 6
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ABSTRACT
A channel router which is to be effective for general-purpose automatic routing must be able to use different sets of routing criteria priorities, in a controllable manner. We present an approach to channel routing with compaction in which channel compaction is adaptable to several routing criteria priorities. We show how overall channel routing performance can be improved by taking advantage of this versatility in channel compaction. We indicate some routing capabilities which cannot be effectively achieved by simply post-processing the output of a traditional gridded channel router. Our solution to this problem is outlined and some results obtained from our router are compared with those of other published channel routers.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Bur83
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Che85
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ellen, H.H., and Kuh, E.S., "A Variable-width Gridless Channel Router", Proc. ICCAD-85, pp. 304-306, 1985.
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Cie82
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Deu76
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Deu85
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Dcutsch, D., "Compacted Channel Routing", Proc. ICCAD- 85, pp. 223-225, 1985.
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Hsu83
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Ked83
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LaP80
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LaPaugh, A., "Algorithms for Integrated Circuit Layout: an Analytic Approach", Ph.D. Thesis, MIT, 1980.
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Pre85
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Riv82
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San84
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Sangiovanni-Vincentelli, A.S., Santomauro, M., and Reed, J., "A New Gridless Channel Router: Yet Another Channel Router the Second (YACR-II)", Proc. ICCAD-84, pp. 72-75, 1984.
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Sch83
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Sou83
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Soukup, J., "Routing on one layer - an algorithm and its implementation", Proceexlings 1983 IEEE International Conference on Computer Design, Port Chester, N.Y., pp 126-135, 1983.
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Szy85
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Szymanski, T.G., "Dogleg Channel Routing is N-P- complete", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-4, No. 1, pp. 31.40, 1985.
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Yos80
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Yoshimum, T. and Kuh, E., "Efficient Algorithms for Channel Routing", U.C. Berkeley Electronics Research Laboratory Memo, No. M80/43, 1980.
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CITED BY 6
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K.-S. The , D. F. Wong , J. Cong, VIA minimization by layout modification, Proceedings of the 26th ACM/IEEE conference on Design automation, p.799-802, June 25-28, 1989, Las Vegas, Nevada, United States
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Toru Awashima , Wataru Yamamoto , Masao Sato , Tatsuo Ohtsuki, An optimal chip compaction method based on shortest path algorithm with automatic jog insertion, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.162-165, November 1992, Santa Clara, California, United States
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