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Reflections of high speed signals analyzed as a delay in timing for clocked logic
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 133 - 139  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
R. E. Canright  Martin Marietta Orlando Aerospace Box 5837, MP 184, Orlando, Florida
A. R. Helland  Westinghouse Electric Corporation Box 1693, MS 1622, Baltimore, Maryland
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 11,   Citation Count: 0
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ABSTRACT

This paper develops equations that can extend the performance of high speed digital systems. The equations allow the application of timing analysis to the selection of the minimum series terminating resistor. Use of the minimum terminating resistor minimizes power dissipation and maximizes the drive capability of the terminated device. Detailed examples simplify the adaptation of these new design procedures to computer-aided design (CAD).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J.A. DeFalco, "Reflection and Crosstalk in Logic Circuit Interconnections," IEEE Spectrum, Vol. 7, No. 7, pp. 44 to 50, July 1970.
 
2
W.R. Blood, Jr., MECL System Design Handbook, 4th Ed., Phoenix, AZ: Motorola Semiconductor, 1983, pp. 52 to 61.
 
3
 
4
R.E. Canright, Jr., "Predicting Effects of Transmission Line Impedance Mismatches," Proc. 36th Electronic Components Conference, May 5 - 7, 1986, Seattle, WA, pp. 169 to 175.
 
5
O.G. Gabbard, "High-Speed Digital Logic for Satellite Communications," Electro- Technology, April 1969, pp. 59 to 65.
 
6
O.A. Horna, "Pulse Reflection in Transmission Lines," IEEE Trans. Computer, Vol. C-20, No. 12, pp. 1558 to 1563, December 1971.
 
7
G.B. Thomas, Jr., Calculus and Analytic Greometry, 4th Ed., Reading MA: Addison- Wesley, 1968, pp. 623 to 624.
 
8
E.E. Davidson and R.D. Lane, "Diodes Damp Line Reflections Without Over- Loading Logic," Electronics, Vol. 49, No. 4, February 19, 1976, pp. 193 to 127.
 
9
A. Barna, High Speed Pulse and Digital Techniques, New York: Wiley Interscience, 1980, pp. 176 to 177.
 
10
R.E. Matick, Transmission Lines for Digital and Communication Networks, New York" McGraw Hill, 1969, pp, 192 to 207.
 
11
Anonymous, FI00K ECL User's Handbook, Puyallup, WA: Fairchild Semiconductor, 1986, pp. 4-12 to 4-14.
 
12
R.L. Morris and J.R. Miller, D eslgnlng with TTL Integrated Circuits, New York, NY: McGraw-Hill, 1971, pp. 25 to 27.

Collaborative Colleagues:
R. E. Canright: colleagues
A. R. Helland: colleagues