Aesop: a tool for automated transistor sizing

ABSTRACT

This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power. These algorithms are implemented in an interactive tool, Aesop. Aesop is a powerful and fast “what-if” tool that allows the designer to explore the space of designs having optimal transistor sizes. When compared to manual designs, the circuits produced by Aesop are typically faster or have substantially lower area and power consumption. Compared to untuned circuits, Aesop typically increases circuit speed by a factor of 2 to 4. Alternatively, power consumption and transistor area can be reduced by 25 — 50% with no sacrifice in circuit speed. These improvements are computed interactively on a professional workstation for circuits containing thousands of transistors.

REFERENCES

• Agul77: B. J. Agule , J. D. Lesser , A. E. Ruehli , P. K. Wolff, An experimental system for power/timing optimization of LSI chips, Proceedings of the 14th conference on Design automation, p.147-152, January 1977
• Crad86: Craddock, R. "Using Aesop for VLSI Circuit Optimization,= unpublished tutorial from the University of Nbrth Carolina. Available from Kye S. Hedlund.
• Fish85: Fishburn, $. mad Dunlop, A. "TILOS: A Posynomial Ap* proach to Transistor Sizing,~ Internation Conf. on Computer Aided Design (1985).
• Gill81: Gill, P.E., Murray, W. and Wright, M.H. Practical Optimization, Academic Press (1981).
• Glas84: Lance A. Glasser , Lennox P.J. Hoyte, Delay and power optimization in VLSI circuits, Proceedings of the 21st conference on Design automation, p.529-535, June 25-27, 1984, Albuquerque, New Mexico, United States
• Hedl87: Hedlund, K.S. "Algorithms and Models for Automated 'transistor Sizing," (in preparation).
• Hedl85: Kye S. Hedlund, Electrical optimization of PLAs, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.681-687, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317963]
• Hedl84: Hedlund, K.S. "Models and Algorithms for Transistor Sizing in MOS Circuits,~ IEEE International Conf. on Computer Aided Design (Oct. 1984) 12-14.
• Joup83: Norman P. Jouppi, Timing analysis for nMOS VLSI, Proceedings of the 20th conference on Design automation, p.411-418, June 27-29, 1983, Miami Beach, Florida, United States
• Lee84: Lee, C.M. and Soukup, H. "An Algorithm for CMOS Timing and Area Optimization,~ J. of Solid-State Circuits, SC- 19, 5 (Oct. 1984), 781-787.
• Marp86: David P. Marple , Abbas El Gamal, Area-delay optimization of programmable logic arrays, Proceedings of the fourth MIT conference on Advanced research in VLSI, p.171-194, June 1986, Cambridge, Massachusetts, United States
• Mats85a: Matson, M.D. "Optimization of Digital MOS VLSI Circuits," 1985 Chapel Hilt Conf. on VLSI (May 1985).
• Nye81: Nye, W., et al. ~DELIGHT: An Optimization-Based Computer-Aided Design System,~ Proc. IEEE international Symp. on Circuits and Systems, (April 1981), 851- 855.
• Oust83: OusterhonL J.K. "Crystal: A Timing Analyzer for nMOS VLSI Circuits,~ Third Caltech Conf. on Very Large ~cale Integration, (Jan. 1983), 57-70.
• Oust84: John K. Ousterhout, Switch-level delay models for digital MOS VLSI, Proceedings of the 21st conference on Design automation, p.542-548, June 25-27, 1984, Albuquerque, New Mexico, United States
• Rueh77: A. E. Ruehli , P. K. Wolff , G. Goertzel, Analytical power/timing optimization technique for digital system, Proceedings of the 14th conference on Design automation, p.142-146, January 1977
• Aubr84: Subramaniam, P. "Table Methods for Timing Simulation,= Custom Integrated Circuits Conf. (1984), 310-314.
• Toku83: Tokuda, T. et.al. "Delay-Time Modeling for ED MOS Logic LSI,~ IEEE Trans. on Computer-Aided Desigr#, CAD-2, 3 (July 1983), 129-134.
• Trim83: 2Xrimberger, S.M. "Automated Performance Optimization of Custom Integrated Circuits,~ VLSI 83, (Aug. 1983), 99-- 108.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  C. Computer Systems Organization

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Experimentation, Measurement, Theory