Architecture and design of the MARS hardware accelerator

ABSTRACT

MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event driven simulations of VLSI circuits. The highly pipelined and parallel architecture of MARS provides a performance comparable to existing hardware simulation engines while its highly flexible architecture supports a wide range of applications. Flexibility is achieved through custom designed microprogrammable and reconfigurable VLSI processors. Logic simulation performance of about one million events per second is easily achievable.

REFERENCES

• 1: T. Blank, "A survey of Hardware Accelerators Used in Computer-Aided Design," IEEE Design and Test of Computers, August 1984, pp. 21-39.
• 2: W. J. Dally and R. E. Bryant, "A Hardware Architecture for Switch-Level Simulation,~ IEEE Transactions on Computer Aided Design, Vol. CAD-4, No. 3, July 1985, pp. 239-50.
• 3: O. Catlin and W. Paseman, "Hardware Acceleration of Logic Simulation Using Data Flow Architecture," Proceedings of the 1985 IEEE International Conference on Computer Design, Santa Clara, CA, November 18-21, 1985, pp. 130-32.
• 4: "Silicon Solutions Carves Niche in VLSI Design," Electronics, August 12, 1985.
• 5: "Powerspice Simulates Circuits Faster and More Accurately," Electronics, August 26, 1985, pp. 50-51.
• 6: P. Agrawal, W. J. Dally, A. K. Ezzat, W. C. Fischer and A. S. Krishnakumar," "MARS: Microprogrammable Accelerator for Rapid Simulations," AT& T Bell Laboratories Internal Technical Memorandum, December 12, 1985.
• 7: P. Agrawal and L. W. Noronha, ~Logie Modeling in the MARS Accelerator," AT& T Bell Laboratories Internal Technical memorandum, August 25, 1986.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

General Terms:
Design, Performance