A hardware switch level simulator for large MOS circuits

ABSTRACT

The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include hardware for simulating pass transistor circuits and for doing timing simulation. By using dynamic RAM for internal list storage, a single HSS processor can accommodate a circuit of up to 262,144 MOS devices. The HSS can be interfaced to a variety of host computers via a general purpose parallel interface, and in its current form offers a 25 times speed improvement compared to MOSSIM II running on a VAX 11-780. Timing mode offers similar speed advantages, with delay calculations that are sufficiently accurate for many simulation tasks.

REFERENCES

• 1: R. E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Transactions on Computers Vo{ C-33 No. 2 Februax)' 1984 pp. 160-177
• 2: W. J. Dally and R. E. Bryant "A Hardware Architecture for Switch-Level Simulation" IEEE Transactions on Computer- Aided Design Vol. CAD-4 No. 3 July 1985 pp. 239-250
• 3: Edward H. Frank, Switch-level simulation of VLSI using a special-purpose data-driven computer, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.735-738, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317972]
• 4: S. Sharma "Switch-Level MOS Simulation on NONVON" Department of Computer Science, Columbia University
• 5: Randal E. Bryant, MOSSIM: A switch-level simulator for MOS LSI, Proceedings of the 18th conference on Design automation, p.786-790, June 29-July 01, 1981, Nashville, Tennessee, United States
• 6: M. T. Smith "Adaptation of a Switch Level Model for Digital Circuits Utiliz!ing Steering Logic" Proceedings of 1he /EEE International Conference on Computer Design 1985 pp. 586- 589
• 7: T. Lin and C. A. Mead "Signal Delay in General ttC Networks" IEEE Transactions on Computer-Aided Design Vol CAD-3 No. 4 October 198~{ pp. 331-349
• 8: W. J. Dally "The MOSSIM Simulation Engine- Architecture and Design" Publication Number 5123:TR:84 Department of Computer Science, California Institute of Technology April 1984
• 9: L. Navel "SPICE 2: A Computer Program to Simulate Semiconductor Circuits" Technical Report ERL-M520 Electronics Research Laboratory, University of California, Berkeley May 1975

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

General Terms:
Design