| A vector hardware accelerator with circuit simulation emphasis |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 24th ACM/IEEE Design Automation Conference
table of contents
Miami Beach, Florida, United States
Pages: 89 - 94
Year of Publication: 1987
ISBN:0-8186-0781-5
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Authors
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A. Vladimirescu
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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D. Weiss
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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M. Katevenis
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Stanford University, Palo Alto, CA
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Z. Bronstein
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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A. Kifir
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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K. Danuwidjaja
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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K. C. Ng.
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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N. Jain
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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S. Lass
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Daisy Systems Corporation, 700 Middlefield Road, Mountain View, CA
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 0
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ABSTRACT
A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance.
The three board accelerator can run the entire application program compiled from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support.
The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance.
The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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---, "ZYCAD Spans the Simulation Spectrum", Application Note, ZYCAD Corp., 1985.
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A.E. Charlesworth, "An Approach to Scientific Array Processing: "the Architectural Design of the AP-120B/FPS-164 Family", Computer, Vol. 14, Sept. 1981.
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W.G. Paseman, and G. Catlin, "The Acceleration of Logic Simulation Using 1~, Data Flow Architecture", Proceedings, Int. Conf. on CAD, Santa Clara, Nov. 1985.
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L.W. Nagel, "SPICE2 - A Computer Program to Simulate Semiconductor Circuits", ERL Memo No. ERL-M520, University of California, Berkeley, May 1975.
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A. Vladimirescu, "LSI Circuit Simulation on Vector Computers", EiRL Memo M82/75, University of California, Berkeley, Oct. 1982.
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F. Ware, L. Lin, R. Wong, B. Woo, C. Hansen, "Fast 64-Bit Chip ',Set Gangs up for Double-Precision Floating-Point Wc~rk", Electronics, Vol. 57, No. 14, July 12, 1984.
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J. White, "Parallelizing Circuit Simulation-A Combined Algorithmic and Specialized Hardware Approach", Proce.edings of the Int. Conference on Computer Design, Rye Brook, NY, Oct. 1986.
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A.R. Newton, and A.L. Sangiovanni-Vincentelli, "Relaxation- Based Electrical Simulation", IEEE Trans. on CAD, Vol, CAD-3, No. 4, Oct. 1984.
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