A case study in silicon compilation software engineering, HVDEV high voltage device layout generator

ABSTRACT

Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper formulates a comparative analysis to conventional layout design accounting for software development and maintenance. Critical factors in planning silicon compilation software development are identified.

REFERENCES

• 1: J. P. Gray, Introduction to silicon compilation, Proceedings of the 16th Conference on Design automation, p.305-306, June 25-27, 1979, San Diego, CA, United States
• 2: N. J. Elias , A. W. Wetzel, The IC Module Compiler, a VLSI system design aid, Proceedings of the 20th conference on Design automation, p.46-49, June 27-29, 1983, Miami Beach, Florida, United States
• 3: John P. Gray , Irene Buchanan , Peter S. Robertson, Designing gate arrays using a silicon compiler, Proceedings of the 19th conference on Design automation, p.377-383, January 1982
• 4: David E. Krekelberg , Gerald E. Sobelman , Chu S. Jhon, Yet another silicon compiler, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.176-182, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317854]
• 5: S. C. Johnscm, "Silicon Compiler Lets System Makers Design Their Own VLSI Chips", Electronic Design, Oct 4, 1984, ppp 167-169.
• 6: M. R. Buric, T. G. Matheson, "Silicon Compilation Environments", Proceedings, Custom Integrated Circuit8 Conference, May 1985.
• 7: S. Dholakia, S. Bush, A. Martinez, (3. Asato, B. Walker, "Compilation of Standard Cell Libraries", Proceedings, Custom Integrated Circuits Conference, May 1986, pp. 343-346.
• 8: Antonio Martínez , Scott Nance, Methodology for compiler generated silicon structures, Proceedings of the 21st conference on Design automation, p.689-691, June 25-27, 1984, Albuquerque, New Mexico, United States
• 9: J. R. Southard, "MacPitts: An Approach to Silicon Compilation", IEEE Computer Magazine, Vol. 16, No. 12, Dec 1983, pp. 74-82.
• 10: A. V. Goldberg, S. S. Hirschhorn, K. J. Lieberrherr, "Approaches Toward Silicon Compilation", IEEE Circuit8 and Device.s Magazine, ~ol. 1, No. 3, May 1983, pp. 29-39.
• 11: N. Bergmann, "A Case Study of the FIRST Silicon Compiler", Third Caltech Conference on VLSI, 1983.
• 12: J. R. Jasica, S. Noujaim, R. Hartley, M. J. Hariman, A Bit-Serial Silicon Compiler", IEEE CCAD-85 Digest of Technical Papers, Santa Clara, CA, Nov 1985, pp. 18-21.
• 13: S. Baker, M. Robinson, "Seattle Silicon Adds Analog Modules; SCI IMP in Pact", Electroni.s Engineering Times, June 23, 1986, p. 12.
• 14: W. J. Helms, K. C. Russell, "Switched Capacitor Filter Compiler", Proceedings, Custom Integrated Circuits Conference, Rochester, NY, May 1986.
• 15: K. Kawauchi, Y. Hatano, J. Ishii, S. Sumi, "A Full-Automated VLSI Layout System Including the Custom Cell Compiler', Proceedings, Custom Integrated Circuits Con ference:, Rochester, NY, May 1986.
• 16: T. K. Ng, M. S. Kaplan, "Silicon Compilation of a Core Microprocessor", Proceedings, Custom Integrated Circuits Con ference, Rochester, N'Y, May 1!}86.
• 17: S. Evanczik, "Silicon Compilers: No Automatic Route to Acceptance", I/LSI Design, Vol. VI, No. 11, Nov 1985, pp. 42-44.
• 18: D. Gajski, R. H. Kuhn, "New VLSI Tools', IEEE Computer Magazine, 1983.
• 19: D. Gajski, "Silicon Compilation", VLSI De,sign, Vol. V'I, No. 11, Nov 1985, pp. 48-64.
• 20: Richard J. Lipton , Stephen C. North , Robert Sedgewick , Jacobo Valdes , Gopalakrishanan Vijayan, ALI: A procedural language to describe VLSI layouts, Proceedings of the 19th conference on Design automation, p.467-474, January 1982
• 21: i. Wacyk, M. Amato, V. Rumennik, "A Power IC with CMOS Analog Control", ISSCC Digest of Technical Papers, Feb 1986.
• 22: S. Golak, B. Singer, E. Stupp, "Lateral DMOS Power Transistor Design", IEEE Electron Device Letter$, Vol. EDL-1, No. 4, April 1980.
• 23: R. J. Bowman, D. J. Lane, "A Knowledge- Based System for Analog Integrated Circuit Design", IEEE 1CCAD-85 Digest of Technical Papers, Santa Clara, CA, Nov 1985.
• 24: F. M. E1-Turky, R. A. Nordin, "BLADES: An Expert System for Analog Circuit Design', Proceedings IEEE International Symposium on Circuit8 and Systems, April 1986.
• 25: Aart J. de Geus, Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.78, July 1986, Las Vegas, Nevada, United States
• 26: William H. Joyner, Jr. , Louise H. Trevillyan , Daniel Brand , Theresa A. Nix , Steven C. Gundersen, Technology adaption in logic synthesis, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.94-100, July 1986, Las Vegas, Nevada, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design