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ESP: a new standard cell placement package using simulated evolution
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 60 - 66  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
R.-M. Kling  Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
P. Banerjee  Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Citation Count: 5
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ABSTRACT

ESP (Evolution-based Standard cell Placement) is a new program package designed to perform standard cell placement and includes macro-block placement capabilities. It uses the new heuristic method of simulating an evolutionary process in order to minimize the cell interconnection wire length. While achieving results comparable to or better than the popular Simulated Annealing algorithm, ESP performs its task about ten times faster.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M.A. Breuer, "Min-C~t Placement'. JouT. Design Automa- H, on and Fault Tolerant Computing, vol. 1. pp. 343-382, Oct. 1977.
 
2
S. Kirkpatrick, C.D. Gelatt, and M.P. Vecchi, "OptimiT~tion by Simulated ,~mnealing', ~, vol. 220, pp. 671-680, May 1983.
 
3
C. Sechen and A.S. Vincentelli, "The TimberWolf Placemerit and Routing Package', Proc. Custom Integrated Circuits Conf., pp. :522-527. May 1984.
 
4
 
5
F. Romeo and A.S. Vincentelli, "Convergence and Finitetime Behavior c,f Simulated Annealing', Proc. 24th Conf. on Dec/s/on and C~uro/, pp. 761-767, Dec. 1985
 
6
M.D. Huang et al., "An efficient general Cooling Schedule for Simulated tmnealing', Proc. ICCAD-86, pp. 381-384.
 
7
A.E. Duntop and B.W. Kerninghan, "A Procedure for Placemerit of Standard cell VLSI CircuitsN, !KEE Trans. on CAD, vo! CAD-1, Jan. 1985
 
8
M. Hanan anal J.M. Kurtzberg, UPlacement TechniquesN. Design Automc~Tn of Digital Systems: Theory and Techn/ques0 vol. 1, chap. 5, Prentice-Hall N.J., pp. 213-282, 1972.
 
9
J.P. Cohoon mad W.D. Paris, mGenetic PlacementN, Proc. ICCAD-86o pp. 422-425.
 
10
R. Otten and L.P.P Ginnekan, "Floor Plan Design using Simulated Annealing', Proc. ICCAD-84, pp. 96-98.
 
11
B. Dunham et al., "Design by Natural Selection', Syrtthese, D. Reidel PubL Comp., Dordrecht-Holland, pp. 254-259, 1963.


Collaborative Colleagues:
R.-M. Kling: colleagues
P. Banerjee: colleagues