An automatic rectilinear partitioning procedure for standard cells

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

An automatic rectilinear partitioning procedure for standard cells

Full text

Pdf (552 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents

Miami Beach, Florida, United States

Pages: 50 - 55

Year of Publication: 1987

ISBN:0-8186-0781-5

Author

M. C. Chi

AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 7

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/37888.37895 What is a DOI?

ABSTRACT

This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&T Bell Laboratories LTX2 chip layout system.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. E. Dunlop and B. W. Kernighan, "A procedure for Layout of Standard-Cell VLSI circuits, IEEE Transactions on Computeraided Design, pp. 02-98 January 1985.
	2	M. Hild, and J. O. Piednoir, "Efficient placement Algorithms for VLSI", VLSI Design, pp. 46-50, Ap ril 1985.
	3	H. Terai et al., "Performance Analysis of Automatic placement and Routing for Large- Scale CMOS Master slices", Proc. of the IEEE International Conference on Computer Design, pp. 536-539, 1983.
	4	R. Putatunda et al., "An optimized and Unique Placement Approach for Very Large Semicustom IC Designs:VLSI in Computers", Proc. of the IEEE International Conference on Computer Design, pp. 440-444, 1985.
	5	B.W. Colbry and J. Soukup, "Layout Aspects of the VLSI Microprocessor Design", Proc. of the IEEE International Symposium on Circuits and Systems, pp. 1214-1228, May 1982
	6	A. E. Dunlop, "Automatic Layout of Gate Arrays", Proc. of the IEEE Symposium on Circuits and Systems, pp. 1245-1248, 1983.
	7	B. W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs", Bell sys. tech. J. Vol. 49, p 291-308, February 1970.
	8	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States

CITED BY 7

	H. Murata , K. Fujiyoshi , M. Kaneko, VLSI/PCB placement with obstacles based on sequence-pair, Proceedings of the 1997 international symposium on Physical design, p.26-31, April 14-16, 1997, Napa Valley, California, United States
	Kalapi Roy , Carl Sechen, A timing driven N-way chip and multi-chip partitioner, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.240-247, November 07-11, 1993, Santa Clara, California, United States
	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	K. Keutzer, DAGON: Technology binding and local optimization by DAG matching, Papers on Twenty-five years of electronic design automation, p.617-624, June 1988
	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States
	C. M. Kyung , J. M. Widder , D. A. Mlynski, Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Keishi Sakanushi , Shigetoshi Nakatake , Yoji Kajitani, The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.267-274, November 08-12, 1998, San Jose, California, United States