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COSMOS: a compiled simulator for MOS circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 9 - 16  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
R. E. Bryant  Carnegie Mellon University
D. Beatty  Carnegie Mellon University
K. Brace  Carnegie Mellon University
K. Cho  Carnegie Mellon University
T. Sheffler  Carnegie Mellon University
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 20,   Citation Count: 55
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ABSTRACT

The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator MOSSIM II.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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R. E. Bryant,, "A Switch-Level Model and Simulator for MOS Digital Systems," IEEE Trans. on Computer8 Vol. C-33, No. 2 (February, 1984), pp. 160-177.
 
3
R. E. Bryant, "Algorithmic Aspects of Symbolic Switch Network Analysis~, IEEE Trans. on Computer-Aided Design of Integrated Circuits, accepted for publication, 1987.
 
4
R. E. Bryant, "Boolean Analysis of MOS Circuits", IEEE Trans. on Computer-Aided Design of Integrated Circuits, accepted for publication, 1987.
 
5
E. Cerny, and J. Gecsei, gSimulation of MOS Circuits by Decision Diagrams~, IEEE Trans. on Computer-Aided Design of Integrated Circuit,, VoL CAD-4, No. 4 (October, 1985), pp. 685-693.
 
6
G. Ditlow, W. Donath, and A. Ruehli, "Logic Equations for MOSFET Circuits", International Symposium on Circuits and Systems, IEEE, 1983, pp. 752-755.
 
7
I.N. Hajj, and D. Saab, "Symbolic Logic Simulation of MOS Circuits~, International Symposium on Circuits and Systems, IEEE, 1983, pp. 246- 249.
 
8
C. E. Shannon, ~A Symbolic Analysis of Relay and Switching Circuits", Trans. of the AIEE, Vol. 57 (1938), pp. 713-723.
 
9
I. SpiUinger, and G. M. Silberman, "Improving the Performance of a Switch-Level Simulator", IEEE Trans. on Computer-Aided Design of Integrated Circuits, Vol. CAD-5, No. 3 (July, 1986), pp. 685-693.
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C. J. Term,n, Simulation Tools for Digital LSI Design, PhD Thesis, MIT Dept. Elec. Eng. and Comp. Sci., October, 1983.

CITED BY  55

Collaborative Colleagues:
R. E. Bryant: colleagues
D. Beatty: colleagues
K. Brace: colleagues
K. Cho: colleagues
T. Sheffler: colleagues