A new verification methodology for complex pipeline behavior

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A new verification methodology for complex pipeline behavior

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 816 - 821

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

Kazuyoshi Kohno	Toshiba Corporation Semiconductor Company, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
Nobu Matsumoto	Toshiba Corporation Semiconductor Company, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 17, Citation Count: 10

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ABSTRACT

A new test program generation tool, mVpGen, is developed for verifying pipeline design of microprocessors. The only inputs mVpGen requires are pipeline-behavior specifications; it automatically generates test cases at first from pipeline-behavior specifications and then automatically generates test programs corresponding to the test cases.Test programs for verifying complex pipeline behavior such as hazard and branch or hazard and exception, are generated. mVpGen has been integrated into a verification system for verifying RTL descriptions of a real microprocessor design and complex bugs that remained hidden in the RTL descriptions are detected.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 10

	Kerstin Eder , Geoff Barrett, Achieving maximum performance: a method for the verification of interlocked pipeline control logic, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jason T. Higgins , Mark D. Aagaard, Simplifying the design and automating the verification of pipelines with structural hazards, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.4, p.651-672, October 2005
	V. Jerinić , D. Müller, Safe integration of parameterized IP, Integration, the VLSI Journal, v.37 n.4, p.193-221, September 2004
	Allon Adir , Hezi Azatchi , Eyal Bin , Ofer Peled , Kirill Shoikhet, A generic micro-architectural test plan approach for microprocessor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Sadik Ezer , Scott Johnson, Smart diagnostics for configurable processor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Heon-Mo Koo , Prabhat Mishra, Test generation using SAT-based bounded model checking for validation of pipelined processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Vasco Jerinić , Jan Langer , Ulrich Heinkel , Dietmar Müller, New methods and coverage metrics for functional verification, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Prabhat Mishra , Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, Proceedings of the conference on Design, Automation and Test in Europe, p.678-683, March 07-11, 2005
	Avi Ziv, Stimuli Generation with Late Binding of Values, Proceedings of the conference on Design, automation and test in Europe, p.10558, February 16-20, 2004
	Heon-Mo Koo , Prabhat Mishra, Functional test generation using design and property decomposition techniques, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.4, p.1-33, July 2009