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Timing driven placement using physical net constraints
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 780 - 783  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
Bill Halpin  Design Technology, Intel, 2200 Mission College, Santa Clara, CA
C. Y. Roger Chen  Syracuse University, Department of EE&CS, Syracuse, NY
Naresh Sehgal  EPD, Intel, 2200 Mission College, Santa Clara, CA
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 28,   Citation Count: 22
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ABSTRACT

This paper presents a new timing driven placement algorithm that explicitly meets physical net lengths constraints. It is the first recursive bi-section placement (RBP) algorithm that meets precise half perimeter bounding box constraints on critical nets. At each level of the recursive bi-section, we use linear programming to ensure that all net constraints are met. Our method can easily be incorporated with existing RBP methods. We use the net constraint based placer to improve timing results by setting and meeting constraints on timing critical nets. We report significantly better timing results on each of the MCNC benchmarks and achieve an average optimization exploitation of 69% versus previously reported 53%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Michael A. B. Jackson, Arvind Srinivasan and E. S. Kuh, "A Fast Algorithm for Performance-Driven Placement," Digest of Technical Papers, ICCAD, pp. 328-331, November 1990.
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Wern-Jieh and Carl Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 349-359, 1995.
 
5
A. Srinivasan, A K. Chaudhary, E. S. Kuh, "RITUAL: Performance Driven Placement Algorithm for Small Cell ICs," ICCAD, pp. 48-51, Nov. 1991.
 
6
Jurgen M. Kleinhans, Georg Sigl, Frank M. Johannes, and Kurt Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization," IEEE Transactions on Computer Aided Design, Volume 10, No. 3 pp. 356-365, 1991.
 
7
K. Doll, F. M. Johannes, and K.J. Antreich, "Iterative placement improvement by network flow methods," IEEE Transactions on CAD, vol. 13 pp.1190-1200, Oct 1994.
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J. Cong, "Timing models for Interconnects and Devices," DAC, 1997.
 
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R.S. Tsay, "Timing-Driven Placement," DAC, 1997.
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Jorge Nocedal and Stephen J. Wright, "Numerical Optimization," Springer-Verlag, 1999.
 
14
H. Paul Williams, "Model Building in Mathematical Programming," John Wiley and Sons, 1999.
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ftp://ftp.es.ele.tue.nl/pub/lp_solve/. Information and Communication Systems group at the Electrical Engineering department of the Eindhoven University of Technology, 1998.
 
18
"www.cbl.ncsu.edu/benchmarks/layoutsynth92/

CITED BY  22

Collaborative Colleagues:
Bill Halpin: colleagues
C. Y. Roger Chen: colleagues
Naresh Sehgal: colleagues