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ABSTRACT
Recursive partitioning based placement has a long history, but there has been little consensus on how cut sequences should be chosen. In this paper, we present a dynamic programming approach to cut sequence generation. If certain assumptions hold, these sequences are optimal. After study of these optimal sequences, we observe that an extremely simple method can be used to construct sequences that are near optimal.Using this method, our bisection based placement tool Feng Shui outperforms the previously presented Capo tool by 11% on a large benchmark. By integrating our cut sequence method into Capo, we are able to improve performance by 5%, bringing the results of Feng Shui and Capo closer together.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266275]
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2
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3
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Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337549]
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4
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|
| |
5
|
[5] A. E. Dunlop and B. W. Kernighan. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-4(1):92-98, January 1985.
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6
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|
 |
7
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|
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8
|
George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266273]
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9
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[9] Brian W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, 49:291-307, 1970.
|
 |
10
|
|
| |
11
|
[11] B. Landman and R. Russo. On a pin versus block relationship for partitioning of logic graphs. IEEE Trans. on Computers, C-20:1469-1479, December 1971.
|
 |
12
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|
| |
13
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|
| |
14
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[14] P. R. Suaris and G. Kedem. An algorithm for quadrisection and its application to standard cell placement. IEEE Trans. on Circuits and Systems, 35(3):394-303, 1988.
|
 |
15
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16
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[16] Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, and Koji Sato. Min-cut placement with global objective functions for large scale sea-of-gates arrays. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 14(4):434-446, April 1995.
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17
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CITED BY 16
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Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Ameya Agnihotri , Mehmet Can YILDIZ , Ateen Khatkhate , Ajita Mathur , Satoshi Ono , Patrick H. Madden, Fractional Cut: Improved Recursive Bisection Placement, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.307, November 09-13, 2003
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