ACM Home Page
Please provide us with feedback. Feedback
Improved cut sequences for partitioning based placement
Full text PdfPdf (47 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 776 - 779  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 19,   Citation Count: 16
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/378239.379064
What is a DOI?

ABSTRACT

Recursive partitioning based placement has a long history, but there has been little consensus on how cut sequences should be chosen. In this paper, we present a dynamic programming approach to cut sequence generation. If certain assumptions hold, these sequences are optimal. After study of these optimal sequences, we observe that an extremely simple method can be used to construct sequences that are near optimal.Using this method, our bisection based placement tool Feng Shui outperforms the previously presented Capo tool by 11% on a large benchmark. By integrating our cut sequence method into Capo, we are able to improve performance by 5%, bringing the results of Feng Shui and Capo closer together.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
3
 
4
 
5
[5] A. E. Dunlop and B. W. Kernighan. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-4(1):92-98, January 1985.
6
7
8
 
9
[9] Brian W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, 49:291-307, 1970.
10
 
11
[11] B. Landman and R. Russo. On a pin versus block relationship for partitioning of logic graphs. IEEE Trans. on Computers, C-20:1469-1479, December 1971.
12
 
13
 
14
[14] P. R. Suaris and G. Kedem. An algorithm for quadrisection and its application to standard cell placement. IEEE Trans. on Circuits and Systems, 35(3):394-303, 1988.
15
 
16
[16] Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, and Koji Sato. Min-cut placement with global objective functions for large scale sea-of-gates arrays. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 14(4):434-446, April 1995.
17

CITED BY  16

Collaborative Colleagues:
Mehmet Can Yildiz: colleagues
Patrick H. Madden: colleagues