A true single-phase 8-bit adiabatic multiplier

ABSTRACT

This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5&mgrm standard CMOS process with an active area of 0.470mm$^2$. Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.

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INDEX TERMS

Primary Classification:
  B. Hardware

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory, Verification

Keywords:
CMOS, SCAL, SCAL-D, VLSI, adiabatic logic, clock generator, dynamic logic, low energy, low power, multiplier, single phase