Coupling-driven bus design for low-power application-specific systems

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Coupling-driven bus design for low-power application-specific systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 750 - 753

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

Youngsoo Shin	Center for Collaborative Research and Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan
Takayasu Sakurai	Center for Collaborative Research and Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 12, Citation Count: 19

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ABSTRACT

In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 20

	Takayasu Sakurai, Minimizing power across multiple technology and design levels, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.24-27, November 10-14, 2002, San Jose, California
	Chun-Gi Lyuh , Taewhan Kim , Ki-Wook Kim, Coupling-aware high-level interconnect synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.609-613, November 10-14, 2002, San Jose, California
	Enrico Macii , Massimo Poncino , Sabino Salerno, Combining wire swapping and spacing for low-power deep-submicron buses, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Maged Ghoneima , Yehea Ismail, Optimum positioning of interleaved repeaters In bidirectional buses, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Harmander S. Deogun , Rajeev R. Rao , Dennis Sylvester , David Blaauw, Leakage-and crosstalk-aware bus encoding for total power reduction, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Maged Ghoneima , Yehea Ismail, Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Puneet Gupta , Andrew B. Kahng , Swamy Muddu, Quantifying Error in Dynamic Power Estimation of CMOS Circuits, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.253-264, March 2005
	Lars Schreiner , Markus Olbrich , Erich Barke , Volker Meyer zu Bexten, Routing of analog busses with parasitic symmetry, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Meeyoung Cha , Chun-Gi Lyuh , Taewhan Kim, Resource-constrained low-power bus encoding with crosstalk delay elimination, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.834-837, January 27-30, 2004, Yokohama, Japan
	Liang Deng , Martin D. F. Wong, Energy optimization in memory address bus structure for application-specific systems, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Masanori Muroyama , Kosuke Tarumi , Koji Makiyama , Hiroto Yasuura, A variation-aware low-power coding methodology for tightly coupled buses, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Lin Xie , Peiliang Qiu , Qinru Qiu, Partitioned bus coding for energy reduction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Debasish Das , Ahmed Shebaita , Yehea Ismail , Hai Zhou , Kip Killpack, NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	M. Ghonemia , Y. Ismail, Formal derivation of optimal active shielding for low-power on-chip buses, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.800-807, November 07-11, 2004
	Karthik Duraisami , Enrico Macii , Massimo Poncino, Energy efficiency bounds of pulse-encoded buses, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	M. Ghoneima , Y. Ismail , M. Khellah , J. Tschanz , V. De, Serial-link bus: a low-power on-chip bus architecture, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.541-546, November 06-10, 2005, San Jose, CA
	Haris Lekatsas , Joerg Henkel, ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.113, January 07-11, 2002
	Konstantin Moiseev , Avinoam Kolodny , Shmuel Wimer, Timing-aware power-optimal ordering of signals, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-17, September 2008
	Maged Ghoneima , Yehea Ismail , Muhammad M. Khellah , James Tschanz , Vivek De, Serial-link bus: a low-power on-chip bus architecture, IEEE Transactions on Circuits and Systems Part I: Regular Papers, v.56 n.9, p.2020-2032, September 2009