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Timing analysis with crosstalk as fixpoints on complete lattice
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 714 - 719  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
Hai Zhou  Advanced Technology Group, Synopsys, Inc., Mountain View
Narendra Shenoy  Advanced Technology Group, Synopsys, Inc., Mountain View
William Nicholls  Advanced Technology Group, Synopsys, Inc., Mountain View
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 7,   Citation Count: 13
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ABSTRACT

Increasing delay variation due to crosstalk has a dramatic impact on deep sub-micron technologies. It is now necessary to include crosstalk in timing analysis. But timing analysis with crosstalk is a chicken-and-egg problem since crosstalk effect in turn depends on timing behavior of a circuit. In this paper, we establish a theoretical foundation for timing analysis with crosstalk. We show that solutions to the problem are fixpoints on a complete lattice. Base on that, we prove in general the convergence of any iterative approach. We also show that, starting from different initial solutions, an iterative approach will reach different fixpoints. The current prevailing practice, which starts from the worst case solution, will always reach the greatest fixpoint (which is the loosest solution). In order to reach the least fixpoint, we need to start from the best case solution. Base on chaotic iteration and heterogeneous structures of coupled circuits, we also design techniques to speed up iterations.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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S. S. Sapatnekar. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing. IEEE Transactions on Computer Aided Design, 2000.
 
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Y. Sasaki and K. Yano. Multi-aggressor relative window method for timing analysis including crosstalk delay degradation. In Custom Integrated Circuit Conference, pages 495-498, 2000.
 
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CITED BY  13

Collaborative Colleagues:
Hai Zhou: colleagues
Narendra Shenoy: colleagues
William Nicholls: colleagues