ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Route packets, not wires: on-chip inteconnection networks
Full text PdfPdf (125 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 684 - 689  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
William J. Dally  Computer Systems Laboratory, Stanford University, Stanford, CA
Brian Towles  Computer Systems Laboratory, Stanford University, Stanford, CA
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 13,   Downloads (12 Months): 117,   Citation Count: 302
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/378239.379048
What is a DOI?

ABSTRACT

Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
"The CoreConnect TM Bus Architecture" IBM, 1999, http://www.chips.ibm.com/products/coreconnect/docs/crcon_wp.pdf.
 
2
W. J. Dally, Virtual-Channel Flow Control, IEEE Transactions on Parallel and Distributed Systems, v.3 n.2, p.194-205, March 1992  [doi>10.1109/71.127260]
 
3
William J. Dally , John W. Poulton, Digital systems engineering, Cambridge University Press, New York, NY, 1998
 
4
MIZUNO,MASAYUKI AND DALLY,WILLIAM J., "Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data," 2001 ISSCC, February, 2001, pp. 346-347.
 
5
"Open Core Protocol TM Data Sheet" Sonics, Inc., http://www.sonicsinc.com/Documents/OpenCoreProtocol_DS.pdf.
 
6
Li-Shiuan Peh , William J. Dally, A Delay Model and Speculative Architecture for Pipelined Routers, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.255, January 20-24, 2001
 
7
Charles L. Seitz, Let's route packets instead of wires, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.133-138, March 1990, Boston, Massachusetts, United States
 
8
VSI Alliance, http://www.vsi.org.

CITED BY  302
Ingrid Verbauwhede , M.-C. Frank Chang, Reconfigurable interconnect for next generation systems, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
Jian Liu , Meigen Shen , Li-Rong Zheng , Hannu Tenhunen, System level interconnect design for network-on-chip using interconnect IPs, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
David Sigüenza-Tortosa , Tapani Ahonen , Jari Nurmi, Issues in the development of a practical NoC: the Proteo concept, Integration, the VLSI Journal, v.38 n.1, p.95-105, October 2004
Vijay Raghunathan , Mani B. Srivastava , Rajesh K. Gupta, A survey of techniques for energy efficient on-chip communication, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
Tajana Simunic , Stephen P. Boyd , Peter Glynn, Managing power consumption in networks on chips, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.96-107, January 2004
Jian Liang , Andrew Laffely , Sriram Srinivasan , Russell Tessier, An architecture and compiler for scalable on-chip communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.711-726, July 2004
Shashi Kumar, On packet switched networks for on-chip communication, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
Praveen Kalla , Xiaobo Sharon Hu , Jörg Henkel, A flexible framework for communication evaluation in SoC design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Li Shang , Li-Shiuan Peh , Niraj K. Jha, PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
JoAnn M. Paul, Programmers' views of SoCs, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
Rutuparna Ramesh Tamhankar , Srinivasan Murali , Giovanni De Micheli, Performance driven reliable link design for networks on chips, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Krishnan Srinivasan , Karam S. Chatha, SAGA: synthesis technique for guaranteed throughput NoC architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Xuning Chen , Li-Shiuan Peh, Leakage power modeling and optimization in interconnection networks, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Maximizing throughput over parallel wire structures in the deep submicrometer regime, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.224-243, April 2003
Jiang Xu , Wayne Wolf, Wave pipelining for application-specific networks-on-chips, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
Cristian Grecu , Partha Pratim Pande , André Ivanov , Res Saleh, Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
Paul Heysters , Gerard Smit , Egbert Molenkamp, A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems, The Journal of Supercomputing, v.26 n.3, p.283-308, November 2003
Axel Jantsch , Hannu Tenhunen, Will networks on chip close the productivity gap?, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
Vishak Venkatraman , Andrew Laffely , Jinwook Jang , Hempraveen Kukkamalla , Zhi Zhu , Wayne Burleson, NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
Feng Zhou , Esther Y. Cheng , Bo Yao , Chung-Kuan Cheng , Ronald Graham, A hierarchical three-way interconnect architecture for hexagonal processors, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
Ian O'Connor, Optical solutions for system-level interconnect, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
Kees Goossens , John Dielissen , Jef van Meerbergen , Peter Poplavko , Andrei Rădulescu , Edwin Rijpkema , Erwin Waterlander , Paul Wielage, Guaranteeing the quality of services in networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
Jongman Kim , Dongkook Park , Chrysostomos Nicopoulos , N. Vijaykrishnan , Chita R. Das, Design and analysis of an NoC architecture from performance, reliability and energy perspective, Proceedings of the 2005 symposium on Architecture for networking and communications systems, October 26-28, 2005, Princeton, NJ, USA
Terry Tao Ye , Luca Benini , Giovanni De Micheli, Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.81-104, February 2004
Jian Liu , Li-Rong Zheng , Hannu Tenhunen, Interconnect intellectual property for network-on-chip (NoC), Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.65-79, February 2004
Praveen Vellanki , Nilanjan Banerjee , Karam S. Chatha, Quality-of-service and error control techniques for network-on-chip architectures, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
Jingcao Hu , Radu Marculescu, DyAD: smart routing for networks-on-chip, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004
Sudarshan Banerjee , Nikil Dutt, FIFO power optimization for on-chip networks, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
Manfred Glesner , Thomas Hollstein , Leandro Soares Indrusiak , Peter Zipf , Thilo Pionteck , Mihail Petrov , Heiko Zimmer , Tudor Murgan, Reconfigurable platforms for ubiquitous computing, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.105-128, February 2004
Tudor Dumitras , Sam Kerner , Radu Marculescu, Enabling on-chip diversity through architectural communication design, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.799-805, January 27-30, 2004, Yokohama, Japan
Raimund Ubar , Jaan Raik, Testing strategies for networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
Giovanni De Micheli, Reliable communication in systems on chips, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
Noel Eisley , Li-Shiuan Peh, High-level power analysis for on-chip networks, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
Cesar Albenes Zeferino , Frederico G. M. E. Santo , Altamiro Amadeu Susin, ParIS: a parameterizable interconnect switch for networks-on-chip, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
P. Avasare , V. Nollet , J-Y. Mignolet , D. Verkest , H. Corporaal, Centralized end-to-end flow control in a best-effort network-on-chip, Proceedings of the 5th ACM international conference on Embedded software, September 18-22, 2005, Jersey City, NJ, USA
Érika Cota , Luigi Carro , Marcelo Lubaszewski, Reusing an on-chip network for the test of core-based systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.471-499, October 2004
Vikas Chandra , Anthony Xu , Herman Schmit, A low power approach to system level pipelined interconnect design, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005
Partha Pratim Pande , Cristian Grecu , Michael Jones , Andre Ivanov , Resve Saleh, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, v.54 n.8, p.1025-1040, August 2005
Girish Varatkar , Radu Marculescu, Traffic analysis for on-chip networks design of multimedia applications, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
Eung S. Shin , Vincent J. Mooney, III , George F. Riley, Round-robin arbiter design and generation, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
A. Leroy , P. Marchal , A. Shickova , F. Catthoor , F. Robert , D. Verkest, Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
John Bainbridge , Steve Furber, Chain: A Delay-Insensitive Chip Area Interconnect, IEEE Micro, v.22 n.5, p.16-23, September 2002
Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Cost considerations in network on chip, Integration, the VLSI Journal, v.38 n.1, p.19-42, October 2004
Dongkun Shin , Jihong Kim, Power-aware communication optimization for networks-on-chips with voltage scalable links, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
Aline Mello , Leonel Tedesco , Ney Calazans , Fernando Moraes, Virtual channels in networks on chip: implementation and evaluation on hermes NoC, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
Ilkka Saastamoinen , David Sigüenza-Tortosa , Jari Nurmi, An IP-based on-chip packet-switched network, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch , Hannu Tenhunen, A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime, Integration, the VLSI Journal, v.38 n.1, p.3-17, October 2004
Girish V. Varatkar , Radu Marculescu, On-chip traffic modeling and synthesis for MPEG-2 video applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.108-119, January 2004
Kuei-Chung Chang , Jih-Sheng Shen , Tien-Fu Chen, A low-power crossroad switch architecture and its core placement for network-on-chip, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
Umit Y. Ogras , Jingcao Hu , Radu Marculescu, Key research problems in NoC design: a holistic perspective, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
Jongman Kim , Dongkook Park , T. Theocharides , N. Vijaykrishnan , Chita R. Das, A low latency router supporting adaptivity for on-chip interconnects, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi, Multi-objective mapping for mesh-based NoC architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
Alexander Maxiaguine , Simon Künzli , Samarjit Chakraborty , Lothar Thiele, Rate analysis for streaming applications with on-chip buffer constraints, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.131-136, January 27-30, 2004, Yokohama, Japan
Andreas Hansson , Kees Goossens , Andrei Rǎdulescu, A unified approach to constrained mapping and routing on network-on-chip architectures, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
César Marcon , André Borin , Altamiro Susin , Luigi Carro , Flávio Wagner, Time and energy efficient mapping of embedded applications onto NoCs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Leonel Tedesco , Aline Mello , Diego Garibotti , Ney Calazans , Fernando Moraes, Traffic generation and performance evaluation for mesh-based NoCs, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
Frédéric Worm , Paolo Ienne , Patrick Thiran , Giovanni De Micheli, A robust self-calibrating transmission scheme for on-chip networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.126-139, January 2005
Tudor Dumitraş , Sam Kerner , Radu Mărculescu, Towards on-chip fault-tolerant communication, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
Seongmoo Heo , Krste Asanović, Replacing global wires with an on-chip network: a power analysis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
Krishnan Srinivasan , Karam S. Chatha, A technique for low energy mapping and routing in network-on-chip architectures, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
Srinivasan Murali , Luca Benini , Giovanni De Micheli, Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Vassos Soteriou , Noel Eisley , Li-Shiuan Peh, Software-directed power-aware interconnection networks, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
Balasubramanian Sethuraman , Prasun Bhattacharya , Jawad Khan , Ranga Vemuri, LiPaR: A light-weight parallel router for FPGA-based networks-on-chip, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
Dong Wu , Bashir M. Al-Hashimi , Marcus T. Schmitz, Improving routing efficiency for network-on-chip through contention-aware input selection, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Manuel Saldaña , Lesley Shannon , Paul Chow, The routability of multiprocessor network topologies in FPGAs, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
Guangyu Chen , Feihui Li , Mahmut Kandemir, Compiler-directed channel allocation for saving power in on-chip networks, ACM SIGPLAN Notices, v.41 n.1, p.194-205, January 2006
Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Mário P. Véstias , Horácio C. Neto, Co-synthesis of a configurable SoC platform based on a network on chip architecture, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Calin Ciordas , Twan Basten , Andrei Rădulescu , Kees Goossens , Jef Van Meerbergen, An event-based monitoring service for networks on chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.4, p.702-723, October 2005
Zhonghai Lu , Axel Jantsch , Ingo Sander, Feasibility analysis of messages for on-chip networks using wormhole routing, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Vasanth Venkatachalam , Michael Franz, Power reduction techniques for microprocessor systems, ACM Computing Surveys (CSUR), v.37 n.3, p.195-237, September 2005
José Carlos S. Palma , César Augusto M. Marcon , Fernando G. Moraes , Ney L. V. Calazans , Ricardo A. L. Reis , Altamiro A. Susin, Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
Robert Mullins , Andrew West , Simon Moore, The design and implementation of a low-latency on-chip network, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Se-Joong Lee , Kangmin Lee , Hoi-Jun Yoo, Analysis and Implementation of Practical, Cost-Effective Networks on Chips, IEEE Design & Test, v.22 n.5, p.422-433, September 2005
Jingcao Hu , Radu Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
Chunsheng Liu , Zach Link , D. K. Pradhan, Reuse-based test access and integrated test scheduling for network-on-chip, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Tobias Bjerregaard , Shankar Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys (CSUR), v.38 n.1, p.1-es, 2006
Hyung Gyu Lee , Umit Y. Ogras , Radu Marculescu , Naehyuck Chang, Design space exploration and prototyping for on-chip multimedia applications, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Kangmin Lee , Se-Joong Lee , Hoi-Jun Yoo, Low-power network-on-chip for high-performance SoC design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.2, p.148-160, February 2006
Umit Y. Ogras , Radu Marculescu , Hyung Gyu Lee , Naehyuck Chang, Communication architecture optimization: making the shortest path shorter in regular networks-on-chip, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Krishnan Srinivasan , Karam S. Chatha , Goran Konjevod, Linear-programming-based techniques for synthesis of network-on-chip architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.4, p.407-420, April 2006
Radu Marculescu , Umit Y. Ogras , Nicholas H. Zamora, Computation and communication refinement for multiprocessor SoC design: A system-level perspective, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.564-592, July 2006
Pete Sedcole , Peter Y. K. Cheung , George A. Constantinides , Wayne Luk, Run-time integration of reconfigurable video processing systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.9, p.1003-1016, September 2007
Mohammad Abdullah Al Faruque , Jörg Henkel, QoS-supported on-chip communication for multi-processors, International Journal of Parallel Programming, v.36 n.1, p.114-139, February 2008
Kuei-Chung Chang , Jih-Sheng Shen , Tien-Fu Chen, Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-31, January 2008
Calin Ciordas , Andreas Hansson , Kees Goossens , Twan Basten, A monitoring-aware network-on-chip design flow, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.397-410, March, 2008
Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi , Davide Patti, A new selection policy for adaptive routing in network on chip, Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications, p.94-99, February 15-17, 2006, Madrid, Spain
Li Shang , Li-Shiuan Peh , Amit Kumar , Niraj K. Jha, Thermal Modeling, Characterization and Management of On-Chip Networks, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.67-78, December 04-08, 2004, Portland, Oregon
Shan Yan , Bill Lin, Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar, A design methodology for application-specific networks-on-chip, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.263-280, May 2006
Zvika Guz , Isask'har Walter , Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Efficient link capacity and QoS design for network-on-chip, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Seung Eun Lee , Nader Bagherzadeh, Increasing the throughput of an adaptive router in network-on-chip (NoC), Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
Noel Eisley , Vassos Soteriou , Li-Shiuan Peh, High-level power analysis for multi-core chips, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
Mohammad Abdullah Al Faruque , Gereon Weiss , Joerg Henkel, Bounded arbitration algorithm for QoS-supported on-chip communication, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
Maurizio Palesi , Rickard Holsmark , Shashi Kumar , Vincenzo Catania, A methodology for design of application specific deadlock-free routing algorithms for NoC systems, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
Leonidas Tsiopoulos , Marina Waldén, Formal development of NoC systems in B, Nordic Journal of Computing, v.13 n.1, p.127-145, June 2006
Luciano Bononi , Nicola Concer, Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
Yuanfang Hu , Yi Zhu , Hongyu Chen , Ronald Graham , Chung-Kuan Cheng, Communication latency aware low power NoC synthesis, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Ming Li , Qing-An Zeng , Wen-Ben Jone, DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Krishnan Srinivasan , Karam S. Chatha, A low complexity heuristic for design of custom network-on-chip architectures, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Guangyu Chen , Feihui Li , Mahmut Kandemir , Mary Jane Irwin, Reducing NoC energy consumption through compiler-directed channel voltage scaling, ACM SIGPLAN Notices, v.41 n.6, June 2006
Kuei-Chung Chang , Jih-Sheng Shen , Tien-Fu Chen, Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Lap-Fai Leung , Chi-Ying Tsui, Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Zhonghai Lu , Mingchen Zhong , Axel Jantsch, Evaluation of on-chip networks using deflection routing, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
Balasubramanian Sethuraman , Ranga Vemuri, optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Umit Y. Ogras , Radu Marculescu, Prediction-based flow control for network-on-chip traffic, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
Alessandro Pinto , Alvise Bonivento , Allberto L. Sangiovanni-Vincentelli , Roberto Passerone , Marco Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.537-563, July 2006
Matteo Monchiero , Gianluca Palermo , Cristina Silvano , Oreste Villa, An efficient synchronization technique for multiprocessor systems on-chip, ACM SIGARCH Computer Architecture News, v.34 n.1, March 2006
Federico Angiolini , Paolo Meloni , Salvatore Carta , Luca Benini , Luigi Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
James Balfour , William J. Dally, Design tradeoffs for tiled CMP on-chip networks, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
Andreas Hansson , Martijn Coenen , Kees Goossens, Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
A. Sheibanyrad , I. Miro Panades , A. Greiner, Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Masaru Takesue, The psi-cube: a bus-based cube-type clustering network for high-performance on-chip systems, Parallel Computing, v.32 n.11-12, p.852-869, December, 2006
Thomas Hollstein , Manfred Glesner, Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms, Computers and Electrical Engineering, v.33 n.4, p.310-319, July, 2007
Ilhan Hatirnaz , Stephane Badel , Nuria Pazos , Yusuf Leblebici , Srinivasan Murali , David Atienza , Giovanni De-Micheli, Early wire characterization for predictable network-on-chip global interconnects, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
Tiberiu Seceleanu, The SegBus platform - architecture and communication mechanisms, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.4, p.151-169, April, 2007
Shehryar Shaheen , Donal Heffernan , Gabriel Leen, A gateway for time-triggered control networks, Microprocessors & Microsystems, v.31 n.1, p.38-50, February, 2007
Umit Y. Ogras , Radu Marculescu, Analysis and optimization of prediction-based flow control in networks-on-chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-28, January 2008
Samuel Evain , Jean-Philippe Diguet , Dominique Houzet, NoC design flow for TDMA and QoS management in a GALS context, EURASIP Journal on Embedded Systems, v.2006 n.1, p.4-4, January 2006
Virginie Fresse , Alain Aubert , Nathalie Bochard, A predictive NoC architecture for vision systems dedicated to image analysis, EURASIP Journal on Embedded Systems, v.2007 n.1, p.36-36, January 2007
Jörg-Christian Niemann , Christoph Puttmann , Mario Porrmann , Ulrich Rückert, Resource efficiency of the GigaNetIC chip multiprocessor architecture, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.5-6, p.285-299, May, 2007
Hyung Gyu Lee , Naehyuck Chang , Umit Y. Ogras , Radu Marculescu, On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-20, August 2007
Jongman Kim , Chrysostomos Nicopoulos , Dongkook Park , Reetuparna Das , Yuan Xie , Vijaykrishnan Narayanan , Mazin S. Yousif , Chita R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
Lin Huang , Feng Yuan , Qiang Xu, On reliable modular testing with vulnerable test access mechanisms, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
Guangyu Chen , Feihui Li , S. W. Son , M. Kandemir, Application mapping for chip multiprocessors, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
Sanjay Rajopadhye , Gautam Gupta , Lakshminarayanan Renganarayana, A domain specific interconnect for reconfigurable computing, ACM SIGPLAN Notices, v.43 n.7, July 2008
Mohammad Abdullah Al Faruque , Rudolf Krist , Jörg Henkel, ADAM: run-time agent-based distributed application mapping for on-chip communication, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
Umit Y. Ogras , Radu Marculescu , Diana Marculescu, Variation-adaptive feedback control for networks-on-chip with multiple clock domains, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
Sotirios G. Ziavras , Alexandros V. Gerbessiotis , Rohan Bafna, Coprocessor design to support MPI primitives in configurable multiprocessors, Integration, the VLSI Journal, v.40 n.3, p.235-252, April, 2007
Guangyu Chen , Feihui Li , Mahmut Kandemir, Compiler-directed application mapping for NoC based chip multiprocessors, ACM SIGPLAN Notices, v.42 n.7, July 2007
Feihui Li , Guangyu Chen , Mahmut Kandemir , Ibrahim Kolcu, Profile-driven energy reduction in network-on-chips, ACM SIGPLAN Notices, v.42 n.6, June 2007
Vassos Soteriou , Noel Eisley , Li-Shiuan Peh, Software-directed power-aware interconnection networks, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.1, p.5-es, March 2007
Akash Kumar , Andreas Hansson , Jos Huisken , Henk Corporaal, Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Tobias Bjerregaard , Mikkel Bystrup Stensgaard , Jens Sparsø, A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Amit Kumar , Li-Shiuan Peh , Partha Kundu , Niraj K. Jha, Express virtual channels: towards the ideal interconnection fabric, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
Shan Tang , Qiang Xu, A multi-core debug platform for NoC-based systems, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Pablo Abad , Valentin Puente , José Angel Gregorio , Pablo Prieto, Rotary router: an efficient architecture for CMP interconnection networks, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
Jiong Luo , Niraj K. Jha , Li-Shiuan Peh, Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.427-437, April 2007
Sami Taktak , Jean-Lou Desbarbieux , Emmanuelle Encrenaz, A tool for automatic detection of deadlock in wormhole networks on chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-22, January 2008
Daniel Barcelos , Eduardo Wenzel Brião , Flávio Rech Wagner, A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
Lesley Shannon , Paul Chow, SIMPPL: an adaptable SoC framework using a programmable controller IP interface to facilitate design reuse, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.377-390, April 2007
Jingcao Hu , R. Marculescu, Application-specific buffer space allocation for networks-on-chip router design, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.354-361, November 07-11, 2004
Robert Mullins , Andrew West , Simon Moore, Low-Latency Virtual-Channel Routers for On-Chip Networks, ACM SIGARCH Computer Architecture News, v.32 n.2, p.188, March 2004
P. Foglia , D. Mangano , C. A. Prete, A cache design for high performance embedded systems, Journal of Embedded Computing, v.1 n.4, p.587-597, December 2005
M. K. F. Schafer , T. Hollstein , H. Zimmer , M. Glesner, Deadlock-free routing and component placement for irregular mesh-based networks-on-chip, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.238-245, November 06-10, 2005, San Jose, CA
U. Y. Ogras , R. Marculescu, Application-specific network-on-chip architecture customization via long-range link insertion, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.246-253, November 06-10, 2005, San Jose, CA
A. DeHon , K. K. Likharev, Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.375-382, November 06-10, 2005, San Jose, CA
K. Srinivasan , K. S. Chatha , G. Konjevod, An automated technique for topology and route generation of application specific on-chip interconnection networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.231-237, November 06-10, 2005, San Jose, CA
Feihui Li , Chrysostomos Nicopoulos , Thomas Richardson , Yuan Xie , Vijaykrishnan Narayanan , Mahmut Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, ACM SIGARCH Computer Architecture News, v.34 n.2, p.130-141, May 2006
Jongman Kim , Chrysostomos Nicopoulos , Dongkook Park, A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks, ACM SIGARCH Computer Architecture News, v.34 n.2, p.4-15, May 2006
Krishnan Srinivasan , Karam S. Chatha, A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures, Proceedings of the 7th International Symposium on Quality Electronic Design, p.352-357, March 27-29, 2006
Praveen Bhojwani , Rabi N. Mahapatra, Core Network Interface Architecture and Latency Constrained On-Chip Communication, Proceedings of the 7th International Symposium on Quality Electronic Design, p.358-363, March 27-29, 2006
Sri Hari Krishna Narayanan , Mahmut Kandemir , Ozcan Ozturk, Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs, Proceedings of the 7th International Symposium on Quality Electronic Design, p.570-575, March 27-29, 2006
Michael R. Marty , Mark D. Hill, Coherence Ordering for Ring-based Chip Multiprocessors, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.309-320, December 09-13, 2006
Chrysostomos A. Nicopoulos , Dongkook Park , Jongman Kim , N. Vijaykrishnan , Mazin S. Yousif , Chita R. Das, ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.333-346, December 09-13, 2006
Girish Varatkar , Radu Marculescu, Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.510, November 09-13, 2003
Adrijean Adriahantenaina , Herve Charlery , Alain Greiner , Laurent Mortiez , Cesar Albenes Zeferino, SPIN: A Scalable, Packet Switched, On-Chip Micro-Network, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20070, March 03-07, 2003
Rami Beidas , Jianwen Zhu, Performance Efficiency of Context-Flow System-on-Chip Platform, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.356, November 09-13, 2003
Youngchul Cho , Ganghee Lee , Sungjoo Yoo , Kiyoung Choi , Nacer-Eddine Zergainoh, Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20132, March 03-07, 2003
Rakesh Kumar , Victor Zyuban , Dean M. Tullsen, Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, ACM SIGARCH Computer Architecture News, v.33 n.2, p.408-419, May 2005
Daeho Seo , Akif Ali , Won-Taek Lim , Nauman Rafique , Mithuna Thottethodi, Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks, ACM SIGARCH Computer Architecture News, v.33 n.2, p.432-443, May 2005
Terry Tao Ye , Luca Benini , Giovanni De Micheli, Packetized On-Chip Interconnect Communication Analysis for MPSoC, Proceedings of the conference on Design, Automation and Test in Europe, p.10344, March 03-07, 2003
E. Rijpkema , K. G. W. Goossens , A. Radulescu , J. Dielissen , J. van Meerbergen , P. Wielage , E. Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.10350, March 03-07, 2003
Jingcao Hu , Radu Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10688, March 03-07, 2003
Tudor Dumitras , Radu Marculescu, On-Chip Stochastic Communication, Proceedings of the conference on Design, Automation and Test in Europe, p.10790, March 03-07, 2003
Luca Carloni , Andrew B. Kahng , Swamy Muddu , Alessandro Pinto , Kambiz Samadi , Puneet Sharma, Interconnect modeling for improved system-level design optimization, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
Daniel Gebhardt , Kenneth S. Stevens, Elastic Flow in an Application Specific Network-on-Chip, Electronic Notes in Theoretical Computer Science (ENTCS), v.200 n.1, p.3-15, February, 2008
Avinash Kodi , Ashwini Sarathy , Ahmed Louri, Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture, Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, December 03-04, 2007, Orlando, Florida, USA
Dietmar Tutsch , Günter Hommel, MLMIN: A multicore processor and parallel computer network topology for multicast, Computers and Operations Research, v.35 n.12, p.3807-3821, December, 2008
Umit Y. Ogras , Radu Marculescu, Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach, Proceedings of the conference on Design, Automation and Test in Europe, p.352-357, March 07-11, 2005
Stergios Stergiou , Federico Angiolini , Salvatore Carta , Luigi Raffo , Davide Bertozzi , Giovanni De Micheli, ×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1188-1193, March 07-11, 2005
V. Nollet , T. Marescaux , P. Avasare , J-Y. Mignolet, Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles, Proceedings of the conference on Design, Automation and Test in Europe, p.234-239, March 07-11, 2005
Tobias Bjerregaard , Jens Sparso, A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.1226-1231, March 07-11, 2005
Wolf-Dietrich Weber , Joe Chou , Ian Swarbrick , Drew Wingard, A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1232-1237, March 07-11, 2005
Hangsheng Wang , Li-Shiuan Peh , Sharad Malik, A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks, Proceedings of the conference on Design, Automation and Test in Europe, p.1238-1243, March 07-11, 2005
Vikas Chandra , Anthony Xu , Herman Schmit , Larry Pileggi, An Interconnect Channel Design Methodology for High Performance Integrated Circuits, Proceedings of the conference on Design, automation and test in Europe, p.21138, February 16-20, 2004
Cesar Marcon , Ney Calazans , Fernando Moraes , Altamiro Susin , Igor Reis , Fabiano Hessel, Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique, Proceedings of the conference on Design, Automation and Test in Europe, p.502-507, March 07-11, 2005
Hangsheng Wang , Li-Shiuan Peh , Sharad Malik, Power-driven Design of Router Microarchitectures in On-chip Networks, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.105, December 03-05, 2003
Matthias Grünewald , Jörg-Christian Niemann , Mario Porrmann , Ulrich Rückert, A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs, Proceedings of the conference on Design, automation and test in Europe, p.20758, February 16-20, 2004
Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar , Tiehan Lv, A Case Study in Networks-on-Chip Design for Embedded Video, Proceedings of the conference on Design, automation and test in Europe, p.20770, February 16-20, 2004
Erland Nilsson , Mikael Millberg , Johnny Oberg , Axel Jantsch, Load Distribution with the Proximity Congestion Awareness in a Network on Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.11126, March 03-07, 2003
Chen-Ling Chou , Radu Marculescu, Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
Cesar Albenes Zeferino , Márcio Eduardo Kreutz , Altamiro Amadeu Susin, RASoC: A Router Soft-Core for Networks-on-Chip, Proceedings of the conference on Design, automation and test in Europe, p.30198, February 16-20, 2004
Andrea Bona , Vittorio Zaccaria , Roberto Zafalon, System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip, Proceedings of the conference on Design, automation and test in Europe, p.30318, February 16-20, 2004
Jingcao Hu , Radu Marculescu, Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints, Proceedings of the conference on Design, automation and test in Europe, p.10234, February 16-20, 2004
Nilanjan Banerjee , Praveen Vellanki , Karam S. Chatha, A Power and Performance Model for Network-on-Chip Architectures, Proceedings of the conference on Design, automation and test in Europe, p.21250, February 16-20, 2004
Andrei Rdulescu , John Dielissen , Kees Goossens , Edwin Rijpkema , Paul Wielage, An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration, Proceedings of the conference on Design, automation and test in Europe, p.20878, February 16-20, 2004
Ingrid Verbauwhede , Patrick Schaumont , Christian Piguet , Bart Kienhuis, Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing, Proceedings of the conference on Design, automation and test in Europe, p.20988, February 16-20, 2004
Mikael Millberg , Erland Nilsson , Rikard Thid , Axel Jantsch, Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20890, February 16-20, 2004
Umit Y. Ogras , Radu Marculescu , Puru Choudhary , Diana Marculescu, Voltage-frequency island partitioning for GALS-based networks-on-chip, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
Leandro Fiorin , Gianluca Palermo , Slobodan Lukovic , Cristina Silvano, A data protection unit for NoC-based architectures, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
Lap-Fai Leung , Chi-Ying Tsui, Energy-aware synthesis of networks-on-chip implemented with voltage islands, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
Edya Ladan-Mozes , Charles E. Leiserson, A consistency architecture for hierarchical shared caches, Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures, June 14-16, 2008, Munich, Germany
Mahmut Kandemir , Ozcan Ozturk, Software-directed combined cpu/link voltage scaling fornoc-based cmps, ACM SIGMETRICS Performance Evaluation Review, v.36 n.1, June 2008
Lei Zhang , Yinhe Han , Qiang Xu , Xiaowei Li, Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Zhou Wenbiao , Yan Zhang , Zhigang Mao, Link-load balance aware mapping and routing for NoC, WSEAS Transactions on Circuits and Systems, v.6 n.11, p.583-591, November 2007
Mohammad Abdullah Al Faruque , Jörg Henkel, Minimizing virtual channel buffer for routers in on-chip communication architectures, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Edgard de Faria Corrêa , Leonardo Alves de Paula e Silva , Flávio Rech Wagner , Luigi Carro, Fitting the router characteristics in NoCs to meet QoS requirements, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
Christian Neeb , Norbert Wehn, Designing efficient irregular networks for heterogeneous systems-on-chip, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.384-396, March, 2008
Praveen S. Bhojwani , Jason D. Lee , Rabi N. Mahapatra, SAPP: scalable and adaptable peak power management in nocs, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
David Atienza , Federico Angiolini , Srinivasan Murali , Antonio Pullini , Luca Benini , Giovanni De Micheli, Invited paper: Network-on-Chip design and synthesis outlook, Integration, the VLSI Journal, v.41 n.3, p.340-359, May, 2008
Assaf Shacham , Keren Bergman , Luca P. Carloni, The case for low-power photonic networks on chip, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
Andreas Hansson , Martijn Coenen , Kees Goossens, Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
Yi Wang , Dan Zhao, The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
Santanu Kundu , Santanu Chattopadhyay, Mesh-of-tree deterministic routing for network-on-chip architecture, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
Rickard Holsmark , Maurizio Palesi , Shashi Kumar, Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.427-440, March, 2008
Sudeep Pasricha , Nikil Dutt, ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
Sander Stuijk , Twan Basten , Marc Geilen , Amir Hossein Ghamarian , Bart Theelen, Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.411-426, March, 2008
Praveen S. Bhojwani , Rabi N. Mahapatra, A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
Abdelkrim Zitouni , Rached Tourki, Arbiter synthesis approach for SoC multi-processor systems, Computers and Electrical Engineering, v.34 n.1, p.63-77, January, 2008
Rahul Nagpal , Arvind Madan , Amrutur Bhardwaj , Y. N. Srikant, INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
Wim Heirman , Joni Dambre , Dirk Stroobandt , Jan Van Campenhout, Rent's rule and parallel programs: characterizing network traffic behavior, Proceedings of the 2008 international workshop on System level interconnect prediction, April 05-08, 2008, Newcastle, United Kingdom
Timothy Mark Pinkston , Jeonghee Shin, Trends toward on-chip networked microsystems, International Journal of High Performance Computing and Networking, v.3 n.1, p.3-18, September 2005
Mohammad Abdullah Al Faruque , Thomas Ebi , Jörg Henkel, Run-time adaptive on-chip communication scheme, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
Pierre Guironnet de Massas , Frédéric Pétrot, Comparison of memory write policies for NoC based multicore cache coherent systems, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Igor Loi , Federico Angiolini , Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
Kristina Kunert , Mattias Weckstén , Magnus Jonsson, Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
Oreste Villa , Gianluca Palermo , Cristina Silvano, Efficiency and scalability of barrier synchronization on NoC based many-core architectures, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
Paul Gratz , Changkyu Kim , Karthikeyan Sankaralingam , Heather Hanson , Premkishore Shivakumar , Stephen W. Keckler , Doug Burger, On-Chip Interconnection Networks of the TRIPS Chip, IEEE Micro, v.27 n.5, p.41-50, September 2007
Yatin Hoskote , Sriram Vangal , Arvind Singh , Nitin Borkar , Shekhar Borkar, A 5-GHz Mesh Interconnect for a Teraflops Processor, IEEE Micro, v.27 n.5, p.51-61, September 2007
Paul Beekhuizen , Dee Denteneer , Jacques Resing, Reduction of a polling network to a single node, Queueing Systems: Theory and Applications, v.58 n.4, p.303-319, April 2008
Avinash Karanth Kodi , Ashwini Sarathy , Ahmed Louri, iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures, ACM SIGARCH Computer Architecture News, v.36 n.3, p.241-250, June 2008
John D. Owens , William J. Dally , Ron Ho , D. N. (Jay) Jayasimha , Stephen W. Keckler , Li-Shiuan Peh, Research Challenges for On-Chip Interconnection Networks, IEEE Micro, v.27 n.5, p.96-108, September 2007
Huaxi Gu , Jiang Xu , Zheng Wang, ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
Suman Kalyan Mandal , Rabi N. Mahapatra, PowerAntz: distributed power sharing strategy for network on chip, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
Igor Loi , Federico Angiolini , Luca Benini, Developing mesochronous synchronizers to enable 3D NoCs, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Lee Kee Goh , Bharadwaj Veeravalli, Design and performance evaluation of combined first-fit task allocation and migration strategies in mesh multiprocessor systems, Parallel Computing, v.34 n.9, p.508-520, September, 2008
Michihiro Koibuchi , Kenichiro Anjo , Yutaka Yamada , Akiya Jouraku , Hideharu Amano, A Simple Data Transfer Technique Using Local Address for Networks-on-Chips, IEEE Transactions on Parallel and Distributed Systems, v.17 n.12, p.1425-1437, December 2006
Nicola Concer , Michele Petracca , Luca P. Carloni, Distributed flit-buffer flow control for networks-on-chip, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
Thomas William Ainsworth , Timothy Mark Pinkston, Characterizing the Cell EIB On-Chip Network, IEEE Micro, v.27 n.5, p.6-14, September 2007
Faizal A. Samman , Thomas Hollstein , Manfred Glesner, Multicast parallel pipeline router architecture for network-on-chip, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Dan Zhao , Yi Wang , Hongyi Wu, Dual-channel binary-countdown medium access control in wireless network-on-chip, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
Simon Ogg , Bashir Al-Hashimi , Alex Yakovlev, Asynchronous transient resilient links for NoC, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
Jun Wang , Hongbo Zeng , Kun Huang , Ge Zhang , Yan Tang, Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Vassos Soteriou , Li-Shiuan Peh, Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks, IEEE Transactions on Parallel and Distributed Systems, v.18 n.3, p.393-408, March 2007
Feng Yuan , Lin Huang , Qiang Xu, Re-examining the use of network-on-chip as test access mechanism, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Shan Tang , Qiang Xu, In-band cross-trigger event transmission for transaction-based debug, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Pejman Lotfi-Kamran , Masoud Daneshtalab , Caro Lucas , Zainalabedin Navabi, BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
Antonio Pullini , Federico Angiolini , Srinivasan Murali , David Atienza , Giovanni De Micheli , Luca Benini, Bringing NoCs to 65 nm, IEEE Micro, v.27 n.5, p.75-85, September 2007
Antonio Pullini , Federico Angiolini , Srinivasan Murali , David Atienza , Giovanni De Micheli , Luca Benini, Bringing NoCs to 65 nm, IEEE Micro, v.27 n.5, p.75-85, September 2007
Ping Zhou , Bo Zhao , Yu Du , Yi Xu , Youtao Zhang , Jun Yang , Li Zhao, Frequent value compression in packet-based NoC architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
Wooyoung Jang , Duo Ding , David Z. Pan, A voltage-frequency island aware energy optimization framework for networks-on-chip, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
S. Jovanović , C. Tanougast , C. Bobda , S. Weber, CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs, Microprocessors & Microsystems, v.33 n.1, p.24-36, February, 2009
Dan Zhao , Yi Wang, MTNet: design of a wireless test framework for heterogeneous nanometer systems-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.8, p.1046-1057, August 2008
Praveen S. Bhojwani , Rabi N. Mahapatra, Robust concurrent online testing of network-on-chip-based SoCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.9, p.1199-1209, September 2008
Praveen Kalla , X. Sharon Hu , Jörg Henkel, A flexible framework for communication evaluation in SoC design, International Journal of Parallel Programming, v.36 n.5, p.457-477, October 2008
Igor Loi , Subhasish Mitra , Thomas H. Lee , Shinobu Fujita , Luca Benini, A low-overhead fault tolerance scheme for TSV-based 3D network on chip links, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
Rostislav (Reuven) Dobkin , Ran Ginosar , Avinoam Kolodny, QNoC asynchronous router, Integration, the VLSI Journal, v.42 n.2, p.103-115, February, 2009
Mohammad Abdullah Al Faruque , Thomas Ebi , Jörg Henkel, ROAdNoC: runtime observability for an adaptive network on chip architecture, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
Vassos Soteriou , Noel Eisley , Hangsheng Wang , Bin Li , Li-Shiuan Peh, Polaris: a system-level roadmapping toolchain for on-chip interconnection networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.855-868, August 2007
Srinivasan Murali , David Atienza , Paolo Meloni , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo, Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.869-880, August 2007
Jongsun Kim , Ingrid Verbauwhede , Mau-Chung Frank Chang, Design of an interconnect architecture and signaling technology for parallelism in communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.881-894, August 2007
Manuel Saldaña , Lesley Shannon , Jia Shuo Yue , Sikang Bian , John Craig , Paul Chow, Routability of network topologies in FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.948-951, August 2007
Yuho Jin , Ki Hwan Yum , Eun Jung Kim, Adaptive data compression for high-performance low-power on-chip networks, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.354-363, November 08-12, 2008
Avinash Karanth Kodi , Ashwini Sarathy , Ahmed Louri , Janet Wang, Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
Taylan Yemliha , Shekhar Srikantaiah , Mahmut Kandemir , Mustafa Karakoy , Mary Jane Irwin, Integrated code and data placement in two-dimensional mesh based chip multiprocessors, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
P. Beekhuizen , T. J. J. Denteneer , J. A. C. Resing, End-to-end delays in polling tree networks, Proceedings of the 3rd International Conference on Performance Evaluation Methodologies and Tools, October 20-24, 2008, Athens, Greece
Daihan Wang , Hiroki Matsutani , Michihiro Koibuchi , Hideharu Amano, A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs, IEICE - Transactions on Information and Systems, v.E90-D n.12, p.1914-1922, December 2007
Woo Joo Kim , Sun Young Hwang, Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.11, p.3297-3303, November 2008
Mohammad Arjomand , Hamid Sarbazi-Azad, A comprehensive power-performance model for NoCs with multi-flit channel buffers, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA
Yi-Jung Chen , Chia-Lin Yang , Yen-Sheng Chang, An architectural co-synthesis algorithm for energy-aware Network-on-Chip design, Journal of Systems Architecture: the EUROMICRO Journal, v.55 n.5-6, p.299-309, May, 2009
Dietmar Tutsch , Miroslaw Malek, Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic, Proceedings of the 2nd International Conference on Simulation Tools and Techniques, March 02-06, 2009, Rome, Italy
Kohei Honda , Vasco T. Vasconcelos , Nobuko Yoshida, Type-Directed Compilation for Multicore Programming, Electronic Notes in Theoretical Computer Science (ENTCS), 241, p.101-111, July, 2009
Yan Pan , Prabhat Kumar , John Kim , Gokhan Memik , Yu Zhang , Alok Choudhary, Firefly: illuminating future network-on-chip with nanophotonics, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
Seung Eun Lee , Nader Bagherzadeh, A variable frequency link for a power-aware network-on-chip (NoC), Integration, the VLSI Journal, v.42 n.4, p.479-485, September, 2009
Nikos Hardavellas , Michael Ferdman , Babak Falsafi , Anastasia Ailamaki, Reactive NUCA: near-optimal block placement and replication in distributed caches, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
Umit Y. Ogras , Radu Marculescu , Diana Marculescu , Eun Gu Jung, Design and management of voltage-frequency island partitioned networks-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.17 n.3, p.330-341, March 2009
Shan Yan , Bill Lin, Custom networks-on-chip architectures with multicast routing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.17 n.3, p.342-355, March 2009
Rosemary Francis , Simon Moore , Robert Mullins, A Network of Time-Division Multiplexed Wiring for FPGAs, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.35-44, April 07-10, 2008
Paul Gratz , Karthikeyan Sankaralingam , Heather Hanson , Premkishore Shivakumar , Robert McDonald , Stephen W. Keckler , Doug Burger, Implementation and Evaluation of a Dynamically Routed Processor Operand Network, Proceedings of the First International Symposium on Networks-on-Chip, p.7-17, May 07-09, 2007
Thomas William Ainsworth , Timothy Mark Pinkston, On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus, Proceedings of the First International Symposium on Networks-on-Chip, p.18-29, May 07-09, 2007
Xiang Wu , Tamer Ragheb , Adnan Aziz , Yehia Massoud, Implementing DSP Algorithms with On-Chip Networks, Proceedings of the First International Symposium on Networks-on-Chip, p.307-316, May 07-09, 2007
Mikkel Bystrup Stensgaard , Jens Sparsø, ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.55-64, April 07-10, 2008
Donghyun Kim , Kwanho Kim , Joo-Young Kim , Seung-Jin Lee , Hoi-Jun Yoo, Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC, Proceedings of the First International Symposium on Networks-on-Chip, p.30-39, May 07-09, 2007
Assaf Shacham , Keren Bergman , Luca P. Carloni, On the Design of a Photonic Network-on-Chip, Proceedings of the First International Symposium on Networks-on-Chip, p.53-64, May 07-09, 2007
Bin Li , Li-Shiuan Peh , Priyadarsan Patra, Impact of Process and Temperature Variations on Network-on-Chip Design Exploration, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.117-126, April 07-10, 2008
Zheng Shi , Alan Burns, Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.161-170, April 07-10, 2008
Itamar Cohen , Ori Rottenstreich , Isaac Keslassy, Statistical Approach to NoC Design, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.171-180, April 07-10, 2008
Pablo Abad , Valentin Puente , Jose Angel Gregorio, Reducing the Interconnection Network Cost of Chip Multiprocessors, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.183-192, April 07-10, 2008
George Michelogiannakis , Dionisios Pnevmatikatos , Manolis Katevenis, Approaching Ideal NoC Latency with Pre-Configured Routes, Proceedings of the First International Symposium on Networks-on-Chip, p.153-162, May 07-09, 2007
S. Bourduas , Z. Zilic, A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing, Proceedings of the First International Symposium on Networks-on-Chip, p.195-204, May 07-09, 2007
Rostislav (Reuven) Dobkin , Ran Ginosar , Israel Cidon, QNoC Asynchronous Router with Dynamic Virtual Channel Allocation, Proceedings of the First International Symposium on Networks-on-Chip, p.218, May 07-09, 2007
Andreas Hansson , Kees Goossens, Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases, Proceedings of the First International Symposium on Networks-on-Chip, p.233-242, May 07-09, 2007
Roman Gindin , Israel Cidon , Idit Keidar, NoC-Based FPGA: Architecture and Routing, Proceedings of the First International Symposium on Networks-on-Chip, p.253-264, May 07-09, 2007
Hiroki Matsutani , Michihiro Koibuchi , Daihan Wang , Hideharu Amano, Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.23-32, April 07-10, 2008
Ying-Cherng Lan , Shih-Hsin Lo , Yueh-Chi Lin , Yu-Hen Hu , Sao-Jie Chen, BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.266-275, May 10-13, 2009
Adan Kohler , Martin Radetzki, Fault-tolerant architecture and deflection routing for degradable NoC switches, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.22-31, May 10-13, 2009
Prabhat Kumar , Yan Pan , John Kim , Gokhan Memik , Alok Choudhary, Exploring concentration and channel slicing in on-chip network router, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.276-285, May 10-13, 2009
Dragomir Milojevic , Luc Montperrus , Diederik Verkest, Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications, Journal of Signal Processing Systems, v.57 n.2, p.139-153, November 2009
Bo Fu , David Wolpert , Paul Ampadu, Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.54-63, May 10-13, 2009
Alexandros Bartzas , Lazaros Papadopoulos , Dimitrios Soudris, A system-level design methodology for application-specific networks-on-chip, Journal of Embedded Computing, v.3 n.3, p.167-177, August 2009
M. Bakhouya , S. Suboh , J. Gaber , T. El-Ghazawi, Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.74-79, May 10-13, 2009
Pavel Ghosh , Arunabha Sen , Alexander Hall, Energy efficient application mapping to NoC processing elements operating at multiple voltage levels, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.80-85, May 10-13, 2009
Luca P. Carloni , Partha Pande , Yuan Xie, Networks-on-chip in emerging interconnect paradigms: Advantages and challenges, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.93-102, May 10-13, 2009
Awet Yemane Weldezion , Matt Grange , Dinesh Pamunuwa , Zhonghai Lu , Axel Jantsch , Roshan Weerasekera , Hannu Tenhunen, Scalability of network-on-chip communication architecture for 3-D meshes, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.114-123, May 10-13, 2009
Robin Emery , Alex Yakovlev , Graeme Chester, Connection-centric network for spiking neural networks, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.144-152, May 10-13, 2009
Nicola Concer , Luciano Bononi , Michael Soulie , Riccardo Locatelli , Luca P. Carloni, CTC: An end-to-end flow control protocol for multi-core systems-on-chip, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.193-202, May 10-13, 2009

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics


General Terms:
Design, Performance, Standardization, Theory

Collaborative Colleagues:
William J. Dally: colleagues
Brian Towles: colleagues

The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player