Micronetwork-based integration for SOCs

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Micronetwork-based integration for SOCs: 673

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Page: 677

Year of Publication: 2001

ISBN:1-58113-297-2

Author

Drew Wingard

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 36

Additional Information:

abstract cited by index terms collaborative colleagues

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ABSTRACT

In this paper, we describe the concept of using an on-chip network as the fundamental communication architecture for a complex SOC design. We describe some of the salient features of a MicroNetwork that we have implemented, and introduce an automated development environment that makes MicroNetwork-based design productive. Finally, we show how one would use our MicroNetwork to integrate an SOC, and provide a general description of several completed MicroNetwork-based designs.

CITED BY 36

	W. Cesário , A. Baghdadi , L. Gauthier , D. Lyonnard , G. Nicolescu , Y. Paviot , S. Yoo , A. A. Jerraya , M. Diaz-Nava, Component-based design approach for multicore SoCs, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Ingrid Verbauwhede , M.-C. Frank Chang, Reconfigurable interconnect for next generation systems, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	Gabriela Nicolescu , Sungjoo Yoo , Aimen Bouchhima , Ahmed Amine Jerraya, Validation in a component-based design flow for multicore SoCs, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Wander O.Cesário , Damien Lyonnard , Gabriela Nicolescu , Yanick Paviot , Sungjoo Yoo , Ahmed A.Jerraya , Lovic Gauthier , Mario Diaz-Nava, Multiprocessor SoC Platforms: A Component-Based Design Approach, IEEE Design & Test, v.19 n.6, p.52-63, November 2002
	Shashi Kumar, On packet switched networks for on-chip communication, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Vijay Raghunathan , Mani B. Srivastava , Rajesh K. Gupta, A survey of techniques for energy efficient on-chip communication, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Partha Pratim Pande , Cristian Grecu , Michael Jones , Andre Ivanov , Resve Saleh, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, v.54 n.8, p.1025-1040, August 2005
	Kees Goossens , John Dielissen , Jef van Meerbergen , Peter Poplavko , Andrei Rădulescu , Edwin Rijpkema , Erwin Waterlander , Paul Wielage, Guaranteeing the quality of services in networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Cristian Grecu , Partha Pratim Pande , André Ivanov , Res Saleh, Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Axel Jantsch , Hannu Tenhunen, Will networks on chip close the productivity gap?, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Praveen Vellanki , Nilanjan Banerjee , Karam S. Chatha, Quality-of-service and error control techniques for mesh-based network-on-chip architectures, Integration, the VLSI Journal, v.38 n.3, p.353-382, January 2005
	Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.105-128, February 2004
	Tiberiu Chelcea , Steven M. Nowick, Robust interfaces for mixed-timing systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.8, p.857-873, August 2004
	Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005
	Sungjoo Yoo , Gabriela Nicolescu , Iuliana Bacivarov , Wassim Youssef , Aimen Bouchhima , Ahmed A. Jerraya, Multi-level software validation for NOC, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Cost considerations in network on chip, Integration, the VLSI Journal, v.38 n.1, p.19-42, October 2004
	Jian Liang , Andrew Laffely , Sriram Srinivasan , Russell Tessier, An architecture and compiler for scalable on-chip communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.711-726, July 2004
	Young-Su Kwon , Jae-Gon Lee , Chong-Min Kyung, Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.806-811, January 27-30, 2004, Yokohama, Japan
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Luca Benini, Application specific NoC design, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar, A design methodology for application-specific networks-on-chip, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.263-280, May 2006
	Srinivasan Murali , David Atienz , Luca Benini , Giovanni De Michel, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Federico Angiolini , Paolo Meloni , Salvatore Carta , Luca Benini , Luigi Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Srinivasan Murali , Paolo Meloni , Federico Angiolini , David Atienza , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo, Designing application-specific networks on chips with floorplan information, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Rami Beidas , Jianwen Zhu, Performance Efficiency of Context-Flow System-on-Chip Platform, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.356, November 09-13, 2003
	Stergios Stergiou , Federico Angiolini , Salvatore Carta , Luigi Raffo , Davide Bertozzi , Giovanni De Micheli, ×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1188-1193, March 07-11, 2005
	Wolf-Dietrich Weber , Joe Chou , Ian Swarbrick , Drew Wingard, A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1232-1237, March 07-11, 2005
	Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Fast exploration of bus-based communication architectures at the CCATB abstraction, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.2, p.1-32, February 2008
	Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar , Tiehan Lv, A Case Study in Networks-on-Chip Design for Embedded Video, Proceedings of the conference on Design, automation and test in Europe, p.20770, February 16-20, 2004
	Dietmar Tutsch , Daniel Lüdtke, Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions, Simulation, v.84 n.2-3, p.61-73, February 2008
	David Atienza , Federico Angiolini , Srinivasan Murali , Antonio Pullini , Luca Benini , Giovanni De Micheli, Invited paper: Network-on-Chip design and synthesis outlook, Integration, the VLSI Journal, v.41 n.3, p.340-359, May, 2008
	Abdelkrim Zitouni , Rached Tourki, Arbiter synthesis approach for SoC multi-processor systems, Computers and Electrical Engineering, v.34 n.1, p.63-77, January, 2008
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	Srinivasan Murali , David Atienza , Paolo Meloni , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo, Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.869-880, August 2007
	Xiang Wu , Tamer Ragheb , Adnan Aziz , Yehia Massoud, Implementing DSP Algorithms with On-Chip Networks, Proceedings of the First International Symposium on Networks-on-Chip, p.307-316, May 07-09, 2007