Addressing the system-on-a-chip interconnect woes through communication-based design

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Addressing the system-on-a-chip interconnect woes through communication-based design

Full text

Pdf (180 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 667 - 672

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

M. Sgroi	University of California at Berkeley, Princeton University
M. Sheets	University of California at Berkeley, Princeton University
A. Mihal	University of California at Berkeley, Princeton University
K. Keutzer	University of California at Berkeley, Princeton University
S. Malik	University of California at Berkeley, Princeton University
J. Rabaey	University of California at Berkeley, Princeton University
A. Sangiovanni-Vencentelli	University of California at Berkeley, Princeton University

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 27, Downloads (12 Months): 118, Citation Count: 75

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/378239.379045 What is a DOI?

ABSTRACT

Communication-based design represents a formal method approach to of system-on-a-chip design that considers communication between components as important as the computations they perform. “Our network-on-chip&rdqo ; approach partitions the communication into layers to maximize reuse and provide a programmer with an abstraction of the underlying communication framework. This layered approach is cast in the structure advocated by the OSI Reference network model and is demonstrated with a reconfigurable DSP example. The Metropolis methodology of deriving layers through a sequence of successive adaptation steps between incompatible behaviors refinement of communication is illustrated through the Intercom a design example. In another approach, MESCAL provides a designer with tools for a correct-by-construction protocol stack.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Felice Balarin , Massimiliano Chiodo , Paolo Giusto , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli , Ellen Sentovich , Kei Suzuki , Bassam Tabbara, Hardware-software co-design of embedded systems: the POLIS approach, Kluwer Academic Publishers, Norwell, MA, 1997
	2	J.-Y. Brunel , W. M. Kruijtzer , H. J. H. N. Kenter , F. Pétrot , L. Pasquier , E. A. de Kock , W. J. M. Smits, COSY communication IP's, Proceedings of the 37th conference on Design automation, p.406-409, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337515]
	3	Cierto VCC, Cadence Design Systems. http://www.cadence.com/technology/hwsw/ciertovcc/
	4	Commercial Video Processors. MIT, Cambridge, MA. http://wad.www.media.mit.edu/people/wad/vsp/node1.html.
	5	T. R. Halfhill. "Intel Network Processor Targets Routers". Microprocessor Report, Vol. 13, September 13, 1999.
	6	C. A. R. Hoare, Communicating sequential processes, Prentice-Hall, Inc., Upper Saddle River, NJ, 1985
	7	M. Horowitz and K. Keutzer. "Hardware-software co-design". In SASIMI'93, October 1993, pp. 5-14.
	8	Norman C. Hutchinson , Larry L. Peterson, The X-Kernel: An Architecture for Implementing Network Protocols, IEEE Transactions on Software Engineering, v.17 n.1, p.64-76, January 1991 [doi>10.1109/32.67579]
	9	K. Keutzer et al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design". IEEE Transactions on Computer-Aided Design. Vol. 19, No. 12. December 2000.
	10	Eddie Kohler , Robert Morris , Benjie Chen , John Jannotti , M. Frans Kaashoek, The click modular router, ACM Transactions on Computer Systems (TOCS), v.18 n.3, p.263-297, Aug. 2000 [doi>10.1145/354871.354874]
	11	Roberto Passerone , James A. Rowson , Alberto Sangiovanni-Vincentelli, Automatic synthesis of interfaces between incompatible protocols, Proceedings of the 35th annual conference on Design automation, p.8-13, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277047]
	12	L. .S. Pen and B. Dally, "Flit-Reservation Flow Control", Proceedings of 6-th International Symposium of Highperformance Computer Architecture, Jan. 2000.
	13	Alberto L. Sangiovanni-Vincentelli , Marco Sgroi , Luciano Lavagno, Formal Models for Communication-Based Design, Proceedings of the 11th International Conference on Concurrency Theory, p.29-47, August 22-25, 2000
	14	J. L. da Silva, Jr. , M. Sgroi , F. De Bernardinis , S. F. Li , A. Sangiovanni-Vincentelli , J. Rabaey, Wireless protocols design: challenges and opportunities, Proceedings of the eighth international workshop on Hardware/software codesign, p.147-151, May 2000, San Diego, California, United States [doi>10.1145/334012.334044]
	15	Sonics Inc. http://www.sonicsinc.com/
	16	VSI Alliance. http://www.vsi.org/
	17	H. Zhang, et al. "A 1-V hererogeneous reconfigurable DSP IC for wireless baseband digital signal processing," IEEE J. Solid State Circuits, vol. 35, Nov. 2000, pp. 1697-1704.
	18	H. Zimmermann, OSI Reference Model - The ISO Model of Architecture for Open Systems Interconnection, IEEE Transactions on Communications COM-28, No. 4: April 1980.

CITED BY 75

	Kees Goossens , John Dielissen , Jef van Meerbergen , Peter Poplavko , Andrei Rădulescu , Edwin Rijpkema , Erwin Waterlander , Paul Wielage, Guaranteeing the quality of services in networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	W. Cesário , A. Baghdadi , L. Gauthier , D. Lyonnard , G. Nicolescu , Y. Paviot , S. Yoo , A. A. Jerraya , M. Diaz-Nava, Component-based design approach for multicore SoCs, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Girish Varatkar , Radu Marculescu, Traffic analysis for on-chip networks design of multimedia applications, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	David Sigüenza-Tortosa , Tapani Ahonen , Jari Nurmi, Issues in the development of a practical NoC: the Proteo concept, Integration, the VLSI Journal, v.38 n.1, p.95-105, October 2004
	Tajana Simunic , Stephen P. Boyd , Peter Glynn, Managing power consumption in networks on chips, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.96-107, January 2004
	Vijay Raghunathan , Mani B. Srivastava , Rajesh K. Gupta, A survey of techniques for energy efficient on-chip communication, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Wander O.Cesário , Damien Lyonnard , Gabriela Nicolescu , Yanick Paviot , Sungjoo Yoo , Ahmed A.Jerraya , Lovic Gauthier , Mario Diaz-Nava, Multiprocessor SoC Platforms: A Component-Based Design Approach, IEEE Design & Test, v.19 n.6, p.52-63, November 2002
	Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Shashi Kumar, On packet switched networks for on-chip communication, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	David Hwang , Bo-Cheng Lai , Patrick Schaumont , Kazuo Sakiyama , Yi Fan , Shenglin Yang , Alireza Hodjat , Ingrid Verbauwhede, Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Xinping Zhu , Sharad Malik, A hierarchical modeling framework for on-chip communication architectures, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.663-671, November 10-14, 2002, San Jose, California
	Jiang Xu , Wayne Wolf, Wave pipelining for application-specific networks-on-chips, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Maximizing throughput over parallel wire structures in the deep submicrometer regime, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.224-243, April 2003
	Axel Jantsch , Hannu Tenhunen, Will networks on chip close the productivity gap?, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Andrew Mihal , Kurt Keutzer, Mapping concurrent applications onto architectural platforms, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Tim Kogel , Malte Doerper , Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Serge Goossens, A modular simulation framework for architectural exploration of on-chip interconnection networks, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	Manfred Glesner , Thomas Hollstein , Leandro Soares Indrusiak , Peter Zipf , Thilo Pionteck , Mihail Petrov , Heiko Zimmer , Tudor Murgan, Reconfigurable platforms for ubiquitous computing, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
	Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004
	Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.105-128, February 2004
	Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Riccardo Locatelli , Giuseppe Maruccia , Francesco Papariello, OCCN: a NoC modeling framework for design exploration, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.129-163, February 2004
	Giovanni Beltrame , Gianluca Palermo , Donatella Sciuto , Cristina Silvano, Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005
	Srinivasan Murali , Giovanni De Micheli, SUNMAP: a tool for automatic topology selection and generation for NoCs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Noel Eisley , Li-Shiuan Peh, High-level power analysis for on-chip networks, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Girish V. Varatkar , Radu Marculescu, On-chip traffic modeling and synthesis for MPEG-2 video applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.108-119, January 2004
	Matthias Gries, Methods for evaluating and covering the design space during early design development, Integration, the VLSI Journal, v.38 n.2, p.131-183, December 2004
	Sungchan Kim , Chaeseok Im , Soonhoi Ha, Schedule-aware performance estimation of communication architecture for efficient design space exploration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.539-552, May 2005
	Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Cost considerations in network on chip, Integration, the VLSI Journal, v.38 n.1, p.19-42, October 2004
	Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch , Hannu Tenhunen, A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime, Integration, the VLSI Journal, v.38 n.1, p.3-17, October 2004
	Noha Mahmoud , Maged Ghoneima , Yehia Ismail, Physical limitations on the bit-rate of on-chip interconnects, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Andreas Hansson , Kees Goossens , Andrei Rǎdulescu, A unified approach to constrained mapping and routing on network-on-chip architectures, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Praveen Vellanki , Nilanjan Banerjee , Karam S. Chatha, Quality-of-service and error control techniques for mesh-based network-on-chip architectures, Integration, the VLSI Journal, v.38 n.3, p.353-382, January 2005
	Seongmoo Heo , Krste Asanović, Replacing global wires with an on-chip network: a power analysis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Nattawut Thepayasuwan , Alex Doboli, Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.525-538, May 2005
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Vasanth Venkatachalam , Michael Franz, Power reduction techniques for microprocessor systems, ACM Computing Surveys (CSUR), v.37 n.3, p.195-237, September 2005
	Andrew Mihal , Chidamber Kulkarni , Matthew Moskewicz , Mel Tsai , Niraj Shah , Scott Weber , Yujia Jin , Kurt Keutzer , Christian Sauer , Kees Vissers , Sharad Malik, Developing Architectural Platforms: A Disciplined Approach, IEEE Design & Test, v.19 n.6, p.6-16, November 2002
	Li Shang , Li-Shiuan Peh , Amit Kumar , Niraj K. Jha, Thermal Modeling, Characterization and Management of On-Chip Networks, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.67-78, December 04-08, 2004, Portland, Oregon
	Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Gunar Schirner , Rainer Dömer, Quantitative analysis of transaction level models for the AMBA bus, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Jiang Xu , Wayne Wolf , Joerg Henkel , Srimat Chakradhar, A design methodology for application-specific networks-on-chip, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.263-280, May 2006
	Gunar Schirner , Rainer Dömer, Accurate yet fast modeling of real-time communication, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Martijn Coenen , Srinivasan Murali , Andrei Ruadulescu , Kees Goossens , Giovanni De Micheli, A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Alessandro Pinto , Alvise Bonivento , Allberto L. Sangiovanni-Vincentelli , Roberto Passerone , Marco Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.537-563, July 2006
	Andreas Hansson , Martijn Coenen , Kees Goossens, Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Gunar Schirner , Rainer Dömer, Fast and accurate transaction level models using result oriented modeling, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Thomas Hollstein , Manfred Glesner, Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms, Computers and Electrical Engineering, v.33 n.4, p.310-319, July, 2007
	Ilhan Hatirnaz , Stephane Badel , Nuria Pazos , Yusuf Leblebici , Srinivasan Murali , David Atienza , Giovanni De-Micheli, Early wire characterization for predictable network-on-chip global interconnects, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Tiberiu Seceleanu, The SegBus platform - architecture and communication mechanisms, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.4, p.151-169, April, 2007
	Umit Y. Ogras , Radu Marculescu, Analysis and optimization of prediction-based flow control in networks-on-chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-28, January 2008
	Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov, Protecting bus-based hardware IP by secret sharing, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Akash Kumar , Andreas Hansson , Jos Huisken , Henk Corporaal, Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Amit Kumar , Li-Shiuan Peh , Partha Kundu , Niraj K. Jha, Express virtual channels: towards the ideal interconnection fabric, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	P. Foglia , D. Mangano , C. A. Prete, A cache design for high performance embedded systems, Journal of Embedded Computing, v.1 n.4, p.587-597, December 2005
	M. K. F. Schafer , T. Hollstein , H. Zimmer , M. Glesner, Deadlock-free routing and component placement for irregular mesh-based networks-on-chip, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.238-245, November 06-10, 2005, San Jose, CA
	Marcello Coppola , Stephane Curaba , Miltos Grammatikakis , Giuseppe Maruccia, IPSIM: SystemC 3.0 Enhancements for Communication Refinement, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20106, March 03-07, 2003
	Kees Goossens , John Dielissen , Om Prakash Gangwal , Santiago Gonzalez Pestana , Andrei Radulescu , Edwin Rijpkema, A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification, Proceedings of the conference on Design, Automation and Test in Europe, p.1182-1187, March 07-11, 2005
	Shankar Mahadevan , Federico Angiolini , Michael Storgaard , Rasmus Grondahl Olsen , Jens Sparso , Jan Madsen, A Network Traffic Generator Model for Fast Network-on-Chip Simulation, Proceedings of the conference on Design, Automation and Test in Europe, p.780-785, March 07-11, 2005
	Hangsheng Wang , Li-Shiuan Peh , Sharad Malik, Power-driven Design of Router Microarchitectures in On-chip Networks, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.105, December 03-05, 2003
	Andrea Bona , Vittorio Zaccaria , Roberto Zafalon, System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip, Proceedings of the conference on Design, automation and test in Europe, p.30318, February 16-20, 2004
	Pierre G. Paulin , Chuck Pilkington , Essaid Bensoudane , Michel Langevin , Damien Lyonnard, Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding, Proceedings of the conference on Design, automation and test in Europe, p.30058, February 16-20, 2004
	Andrei Rdulescu , John Dielissen , Kees Goossens , Edwin Rijpkema , Paul Wielage, An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration, Proceedings of the conference on Design, automation and test in Europe, p.20878, February 16-20, 2004
	Mikael Millberg , Erland Nilsson , Rikard Thid , Axel Jantsch, Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20890, February 16-20, 2004
	Zhonghai Lu , Ming Liu , Axel Jantsch, Layered switching for networks on chip, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Yen-Kuang Chen , S. Y. Kung, Trend and Challenge on System-on-a-Chip Designs, Journal of Signal Processing Systems, v.53 n.1-2, p.217-229, November 2008
	Timothy Mark Pinkston , Jeonghee Shin, Trends toward on-chip networked microsystems, International Journal of High Performance Computing and Networking, v.3 n.1, p.3-18, September 2005
	Robertas Damaševičius , Vytautas Štuikys, Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming, Informatica, v.14 n.1, p.3-18, January 2003
	Gunar Schirner , Rainer Dömer, Quantitative analysis of the speed/accuracy trade-off in transaction level modeling, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.1, p.1-29, December 2008
	Huaxi Gu , Jiang Xu , Zheng Wang, ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
	Srinivasan Murali , David Atienza , Paolo Meloni , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo, Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.869-880, August 2007
	Katalin Popovici , Ahmed Jerraya, Flexible and abstract communication and interconnect modeling for MPSoC, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Thomas William Ainsworth , Timothy Mark Pinkston, On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus, Proceedings of the First International Symposium on Networks-on-Chip, p.18-29, May 07-09, 2007
	Kees Goossens , Martijn Bennebroek , Jae Young Hur , Muhammad Aqeel Wahlah, Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.45-54, April 07-10, 2008
	Xiang Wu , Tamer Ragheb , Adnan Aziz , Yehia Massoud, Implementing DSP Algorithms with On-Chip Networks, Proceedings of the First International Symposium on Networks-on-Chip, p.307-316, May 07-09, 2007
	Andreas Hansson , Kees Goossens, Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases, Proceedings of the First International Symposium on Networks-on-Chip, p.233-242, May 07-09, 2007