A transaction-based unified simulation/emulation architecture for functional verification

ABSTRACT

A transaction-based layered architecture providing for 100% portability of a C-based testbench between simulation and emulation is proposed. Transaction-based communication results in performance which is commensurate with emulation without a hardware target. Testbench portability eliminates duplicated effort when combining system level simulation and emulation. An implementation based on the IKOS VStation emulator validates these architectural claims on real designs.

REFERENCES

• 1: "PCI Local Bus Specification, Revision 2.1". PCISig, 1995.
• 2: Jerry Bauer , Michael Bershteyn , Ian Kaplan , Paul Vyedin, A reconfigurable logic machine for fast event-driven simulation, Proceedings of the 35th annual conference on Design automation, p.668-671, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277214]
• 3: Françoise Casaubieilh , Anthony McIsaac , Mike Benjamin , Mike Bartley , François Pogodalla , Frédéric Rocheteau , Mohamed Belhadj , Jeremy Eggleton , Gérard Mas , Geoff Barrett , Christian Berthet, Functional verification methodology of Chameleon processor, Proceedings of the 33rd annual conference on Design automation, p.421-426, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240599]
• 4: Benoit Clement , Richard Hersemeule , Etienne Lantreibecq , Bernard Ramanadin , Pierre Coulomb , Francois Pogodalla, Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.420-424, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309971]
• 5: Adrian Evans , Allan Silburt , Gary Vrckovnik , Thane Brown , Mario Dufresne , Geoffrey Hall , Tung Ho , Ying Liu, Functional verification of large ASICs, Proceedings of the 35th annual conference on Design automation, p.650-655, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277210]
• 6: Gopi Ganapathy , Ram Narayan , Glenn Jorden , Denzil Fernandez , Ming Wang , Jim Nishimura, Hardware emulation for functional verification of K5, Proceedings of the 33rd annual conference on Design automation, p.315-318, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240578]
• 7: Michael Katrowitz , Lisa M. Noack, I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor, Proceedings of the 33rd annual conference on Design automation, p.325-330, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240580]
• 8: Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277084]
• 9: James Monaco , David Holloway , Rajesh Raina, Functional verification methodology for the PowerPC 604 microprocessor, Proceedings of the 33rd annual conference on Design automation, p.319-324, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240579]
• 10: Val Popescu , Bill McNamara, Innovative verification strategy reduces design cycle time for high-end SPARC processor, Proceedings of the 33rd annual conference on Design automation, p.311-314, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240577]
• 11: Benny Schnaider , Einat Yogev, Software development in a hardware simulation environment, Proceedings of the 33rd annual conference on Design automation, p.684-689, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240647]
• 12: W. Richard Stevens, UNIX Network Programming: Networking APIs: Sockets and XTI, Prentice Hall PTR, Upper Saddle River, NJ, 1997

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Experimentation, Measurement, Performance, Theory, Verification