| Fast power/ground network optimization based on equivalent circuit modeling |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 38th annual Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 550 - 554
Year of Publication: 2001
ISBN:1-58113-297-2
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Downloads (6 Weeks): 7, Downloads (12 Months): 22, Citation Count: 14
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ABSTRACT
This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints. Instead of solving the original power/ground networks extracted from circuit layouts as previous methods did, the new method first builds the equivalent models for many series resistors in the original networks, then the sequence of linear programming method [9] is used to solve the simplified networks. The solutions of the original networks then are back solved from the optimized, simplified networks. The new algorithm simply exploits the regularities in the power/ground networks. Experimental results show that the complexities of simplified networks are typically significantly smaller than that of the original circuits, which renders the new algorithm extremely fast. For instance, power/ground networks with more than one million branches can be sized in a few minutes on modern SUN workstations.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Xiang-Dong Tan , C.-J. Richard Shi , Dragos Lungeanu , Jyh-Chwen Lee , Li-Pen Yuan, Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings, Proceedings of the 36th ACM/IEEE conference on Design automation, p.78-83, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309880]
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CITED BY 14
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Yici Cai , Zhu Pan , Shelton X-D Tan , Xianlong Hong , Wenting Hou , Lifeng Wu, Relaxed hierarchical power/ground grid analysis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Jingjing Fu , Zuying Luo , Xianlong Hong , Yici Cai , Sheldon X.-D. Tan , Zhu Pan, A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.505-510, January 27-30, 2004, Yokohama, Japan
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Yici Cai , Jin Shi , Zhu Pan , Xianlong Hong , Sheldon X. -D. Tan, Large scale P/G grid transient simulation using hierarchical relaxed approach, Integration, the VLSI Journal, v.41 n.1, p.153-160, January, 2008
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