| Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 38th annual Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 518 - 523
Year of Publication: 2001
ISBN:1-58113-297-2
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Authors
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Damien Lyonnard
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SLS Group, TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
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Sungjoo Yoo
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SLS Group, TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
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Amer Baghdadi
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SLS Group, TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
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Ahmed A. Jerraya
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SLS Group, TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
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Downloads (6 Weeks): 8, Downloads (12 Months): 87, Citation Count: 43
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ABSTRACT
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two system examples show the effectiveness of the presented design flow.
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Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 43
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Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed A. Jerraya, A generic wrapper architecture for multi-processor SoC cosimulation and design, Proceedings of the ninth international symposium on Hardware/software codesign, p.195-200, April 2001, Copenhagen, Denmark
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Samy Meftali , Ferid Gharsalli , Frederic Rousseau , Ahmed A. Jerraya, An optimal memory allocation for application-specific multiprocessor system-on-chip, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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Wander O.Cesário , Damien Lyonnard , Gabriela Nicolescu , Yanick Paviot , Sungjoo Yoo , Ahmed A.Jerraya , Lovic Gauthier , Mario Diaz-Nava, Multiprocessor SoC Platforms: A Component-Based Design Approach, IEEE Design & Test, v.19 n.6, p.52-63, November 2002
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Férid Gharsalli , Damien Lyonnard , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
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W. Cesário , A. Baghdadi , L. Gauthier , D. Lyonnard , G. Nicolescu , Y. Paviot , S. Yoo , A. A. Jerraya , M. Diaz-Nava, Component-based design approach for multicore SoCs, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Jaehwan Lee , Vincent John Mooney, III , Anders Daleby , Karl Ingström , Tommy Klevin , Lennart Lindh, A comparison of the RTU hardware RTOS with a hardware/software RTOS, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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Dongwan Shin , Andreas Gerstlauer , Rainer Dömer , Daniel D. Gajski, Automatic network generation for system-on-chip communication design, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
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Sudeep Pasricha , Nikil Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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M. Anouar Dziri , Firaz Samet , Flavio Rech Wagner , Wander O. Cesário , Ahmed A. Jerraya, Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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Dongwan Shin , Andreas Gerstlauer , Junyu Peng , Rainer Dömer , Daniel D. Gajski, Automatic generation of transaction level models for rapid design space exploration, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
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Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau , Milind Girkarmark , Xinmin Tian , Hideki Saito, Challenges in exploitation of loop parallelism in embedded applications, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
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Mark Thompson , Hristo Nikolov , Todor Stefanov , Andy D. Pimentel , Cagkan Erbas , Simon Polstra , Ed F. Deprettere, A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
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H. Nikolov , M. Thompson , T. Stefanov , A. Pimentel , S. Polstra , R. Bose , C. Zissulescu , E. Deprettere, Daedalus: toward composable multimedia MP-SoC design, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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Rainer Dömer , Andreas Gerstlauer , Junyu Peng , Dongwan Shin , Lukai Cai , Haobo Yu , Samar Abdi , Daniel D. Gajski, System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design, EURASIP Journal on Embedded Systems, v.2008 n.3, p.1-13, January 2008
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