A semi-custom design flow in high-performance microprocessor design

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A semi-custom design flow in high-performance microprocessor design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 426 - 431

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

Gregory A. Northrop	IBM Research, Yorktown Heights, NY
Pong-Fei Lu	IBM Research, Yorktown Heights, NY

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 20, Citation Count: 8

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Averill, R.M. et. al., Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors. IBM Journal of Research and Development, 43, 1999, 681-706.
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CITED BY 8

	Andrew R. Conn , Chandu Visweswariah, Overview of continuous optimization advances and applications to circuit tuning, Proceedings of the 2001 international symposium on Physical design, p.74-81, April 01-04, 2001, Sonoma, California, United States
	Leon Stok , John Cohn, There is life left in ASICs, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Miodrag Vujkovic , Carl Sechen, Optimized power-delay curve generation for standard cell ICs, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.387-394, November 10-14, 2002, San Jose, California
	Baohua Wang , Pinaki Mazumder, Optimization of circuit trajectories: an auxiliary network approach, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Masanori Hashimoto , Kazunori Fujimori , Hidetoshi Onodera, Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Miodrag Vujkovic , David Wadkins , Bill Swartz , Carl Sechen, Efficient timing closure without timing driven placement and routing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Matthew M. Ziegler , Gary S. Ditlow , Stephen V. Kosonocky , Zhenyu (Jerry) Qi , Mircea R. Stan, Structured and tuned array generation (STAG) for high-performance random logic, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Beibei Ren , Anru Wang , Joyopriya Bakshi , Kai Liu , Wei Li , Wayne Dai, A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications, Proceedings of the conference on Design, automation and test in Europe, p.30280, February 16-20, 2004